Highly Scalable On-the-Fly Interleaved Address Generation for UMTS/HSPA+ Parallel Turbo Decoder

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dc.citation.conferenceDate2013en_US
dc.citation.conferenceName24th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2013)en_US
dc.citation.firstpage356en_US
dc.citation.lastpage362en_US
dc.citation.locationWashington, DCen_US
dc.contributor.authorVosoughi, Aidaen_US
dc.contributor.authorWang, Guohuien_US
dc.contributor.authorShen, Haoen_US
dc.contributor.authorCavallaro, Joseph R.en_US
dc.contributor.authorGuo, Yuanbinen_US
dc.contributor.orgCMCen_US
dc.date.accessioned2013-10-25T14:45:43Zen_US
dc.date.available2013-10-25T14:45:43Zen_US
dc.date.issued2013-06-01en_US
dc.description.abstractHigh throughput parallel interleaver design is a major challenge in designing parallel turbo decoders that conform to high data rate requirements of advanced standards such as HSPA+. The hardware complexity of the HSPA+ interleaver makes it difficult to scale to high degrees of parallelism. We propose a novel algorithm and architecture for on-the-fly parallel interleaved address generation in UMTS/HSPA+ standard that is highly scalable. Our proposed algorithm generates an interleaved memory address from an original input address without building the complete interleaving pattern or storing it; the generated interleaved address can be used directly for interleaved writing to memory blocks. We use an extended Euclidean algorithm for modular multiplicative inversion as a step towards reversed intra-row permutations in UMTS/HSPA+ standard. As a result, we can determine interleaved addresses from original addresses. We also propose an efficient and scalable hardware architecture for our method. Our design generates 32 interleaved addresses in one cycle and satisfies the data rate requirement of 672 Mbps in HSPA+ while the silicon area and frequency is improved compared to recent related works.en_US
dc.description.sponsorshipHuaweien_US
dc.description.sponsorshipUS National Science Foundationen_US
dc.identifier.citationA. Vosoughi, G. Wang, H. Shen, J. R. Cavallaro and Y. Guo, "Highly Scalable On-the-Fly Interleaved Address Generation for UMTS/HSPA+ Parallel Turbo Decoder," 2013.en_US
dc.identifier.doihttp://dx.doi.org/10.1109/ASAP.2013.6567601en_US
dc.identifier.otherhttp://www.computer.org/csdl/proceedings/asap/2013/0494/00/06567601-abs.htmlen_US
dc.identifier.otherhttp://doi.ieeecomputersociety.org/10.1109/ASAP.2013.6567601en_US
dc.identifier.urihttps://hdl.handle.net/1911/75001en_US
dc.language.isoengen_US
dc.publisher24th IEEE International Conference on Application-specific Systems, Architectures and Processorsen_US
dc.subjectTurbo decoderen_US
dc.subjectParallel turbo decoderen_US
dc.subjectHSPA+en_US
dc.subjectUMTSen_US
dc.subjectInterleaved writingen_US
dc.subjectInterleaved Address Generationen_US
dc.titleHighly Scalable On-the-Fly Interleaved Address Generation for UMTS/HSPA+ Parallel Turbo Decoderen_US
dc.typeConference paperen_US
dc.type.dcmiTexten_US
dc.type.dcmiTexten_US
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