Channel Equalization Algorithms for MIMO Downlink and ASIP Architectures
| dc.citation.bibtexName | mastersthesis | en_US |
| dc.citation.journalTitle | Masters Thesis | en_US |
| dc.citation.location | Houston, TX | en_US |
| dc.contributor.org | Center for Multimedia Communications (http://cmc.rice.edu/) | en_US |
| dc.creator | Radosavljevic, Predrag | en_US |
| dc.date.accessioned | 2007-10-31T00:58:13Z | en_US |
| dc.date.available | 2007-10-31T00:58:13Z | en_US |
| dc.date.issued | 2004-04-01 | en_US |
| dc.date.modified | 2004-08-30 | en_US |
| dc.date.submitted | 2004-05-14 | en_US |
| dc.description | Masters Thesis | en_US |
| dc.description.abstract | Processors for mobile handsets in 3G cellular systems require: high speed, flexibility and low power dissipation. While computationally efficient, ASIC processors are often not flexible enough to support necessary variations of implemented algorithms. On the other hand, programmable DSP processors are not optimized for a specific application and often they are not able to achieve high performance with low power dissipation. As a solution we exploit programmable architectures with possibility for customization - Application Specific Instruction set Processors (ASIPs). Channel equalization based on iterative Conjugate Gradient and Least Mean Square algorithms and several algorithmic modifications are implemented in MIMO context on the same ASIPs based on Transport Triggered Architecture. Customization of ASIPs is achieved by extending the instruction set with application-specific operations. Identical customized ASIP architecture can achieve 3GPP real-time requirements in broad range of channel environments and for different equalization algorithms with reasonable clock frequency and low power dissipation. | en_US |
| dc.description.sponsorship | Nokia | en_US |
| dc.description.sponsorship | Nokia/Texas Instruments | en_US |
| dc.identifier.citation | "Channel Equalization Algorithms for MIMO Downlink and ASIP Architectures," <i>Masters Thesis,</i> 2004. | en_US |
| dc.identifier.uri | https://hdl.handle.net/1911/20204 | en_US |
| dc.language.iso | eng | en_US |
| dc.subject | Chip-level equalization | en_US |
| dc.subject | MIMO | en_US |
| dc.subject | Conjugate Gradient | en_US |
| dc.subject | ASIP | en_US |
| dc.subject | TTA | en_US |
| dc.subject.keyword | Chip-level equalization | en_US |
| dc.subject.keyword | MIMO | en_US |
| dc.subject.keyword | Conjugate Gradient | en_US |
| dc.subject.keyword | ASIP | en_US |
| dc.subject.keyword | TTA | en_US |
| dc.title | Channel Equalization Algorithms for MIMO Downlink and ASIP Architectures | en_US |
| dc.type | Thesis | en_US |
| dc.type.dcmi | Text | en_US |
| thesis.degree.level | Masters | en_US |