A Customized MVA Model for ILP Multiprocessors

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dc.citation.bibtexNametechreporten_US
dc.citation.issueNumber1369en_US
dc.citation.journalTitleUniversity of Wisconsin-Madison Computer Sciences Technical Reporten_US
dc.contributor.authorSorin, Daniel J.en_US
dc.contributor.authorVernon, Mary K.en_US
dc.contributor.authorPai, Vijay S.en_US
dc.contributor.authorAdve, Sarita V.en_US
dc.contributor.authorWood, David A.en_US
dc.contributor.orgCITI (http://citi.rice.edu/)en_US
dc.date.accessioned2007-10-31T01:06:24Zen_US
dc.date.available2007-10-31T01:06:24Zen_US
dc.date.issued1998-04-20en_US
dc.date.modified2003-07-12en_US
dc.date.submitted2002-03-20en_US
dc.descriptionTech Reporten_US
dc.description.abstractThis paper provides the customized MVA equations for an analytical model for evaluating architectural alternatives for shared-memory multiprocessors with processors that aggressively exploit instruction-level parallelism (ILP). Compared to simulation, the analytical model is many orders of magnitude faster to solve, yielding highly accurate system performance estimates in seconds.en_US
dc.identifier.citationD. J. Sorin, M. K. Vernon, V. S. Pai, S. V. Adve and D. A. Wood, "A Customized MVA Model for ILP Multiprocessors," <i>University of Wisconsin-Madison Computer Sciences Technical Report,</i> no. 1369, 1998.en_US
dc.identifier.urihttps://hdl.handle.net/1911/20380en_US
dc.language.isoengen_US
dc.subjectanalytical modelingen_US
dc.subjectshared-memory multiprocessorsen_US
dc.subjectinstruction-level parallelismen_US
dc.subject.keywordanalytical modelingen_US
dc.subject.keywordshared-memory multiprocessorsen_US
dc.subject.keywordinstruction-level parallelismen_US
dc.titleA Customized MVA Model for ILP Multiprocessorsen_US
dc.typeReporten_US
dc.type.dcmiTexten_US
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