CORDIC Arithmetic for an SVD Processor
| dc.citation.conferenceDate | 1987 | en_US |
| dc.citation.conferenceName | IEEE 8th Symposium on Computer Arithmetic | en_US |
| dc.citation.firstpage | 113 | |
| dc.citation.lastpage | 120 | |
| dc.citation.location | Como, Italy | en_US |
| dc.contributor.author | Cavallaro, Joseph R. | |
| dc.contributor.author | Luk, Franklin T. | |
| dc.contributor.org | Center for Multimedia Communication | en_US |
| dc.date.accessioned | 2012-05-25T16:44:28Z | |
| dc.date.available | 2012-05-25T16:44:28Z | |
| dc.date.issued | 1987-05-01 | eng |
| dc.description.abstract | Arithmetic issues in the calculation of the Singular Value Decomposition (SVD) are discussed. Traditional algorithms using hardware division and square root are replaced with the special purpose CORDIC algorithms for computing vector rotations and inverse tangents. The CORDIC 2 x 2 SVD processor can be twice as fast as one assembled from traditional hardware units. A prototype VLSI implementation of a CORDIC SVD processor array is planned for use in real-time signal processing applications. | en_US |
| dc.description.sponsorship | Army Research Office | en_US |
| dc.description.sponsorship | Cornell Program on Submicrometer Structures | en_US |
| dc.identifier.citation | J. R. Cavallaro and F. T. Luk, "CORDIC Arithmetic for an SVD Processor," 1987. | * |
| dc.identifier.doi | http://dx.doi.org/10.1109/ARITH.1987.6158686 | en_US |
| dc.identifier.other | http://scholar.google.com/scholar?cluster=2454426890384439275&hl=en&as_sdt=0,44 | |
| dc.identifier.uri | https://hdl.handle.net/1911/64179 | |
| dc.language.iso | eng | en |
| dc.publisher | The Computer Society of the IEEE | en_US |
| dc.subject | Singular Value Decomposition (SVD) | en_US |
| dc.subject | CORDIC | en_US |
| dc.subject | VLSI | en_US |
| dc.title | CORDIC Arithmetic for an SVD Processor | en_US |
| dc.type | Conference paper | en_US |
| dc.type.dcmi | Text | en |
| dc.type.dcmi | Text | en_US |