CORDIC Arithmetic for an SVD Processor

dc.citation.conferenceDate1987en_US
dc.citation.conferenceNameIEEE 8th Symposium on Computer Arithmeticen_US
dc.citation.firstpage113en_US
dc.citation.lastpage120en_US
dc.citation.locationComo, Italyen_US
dc.contributor.authorCavallaro, Joseph R.en_US
dc.contributor.authorLuk, Franklin T.en_US
dc.contributor.orgCenter for Multimedia Communicationen_US
dc.date.accessioned2012-05-25T16:44:28Zen_US
dc.date.available2012-05-25T16:44:28Zen_US
dc.date.issued1987-05-01en_US
dc.description.abstractArithmetic issues in the calculation of the Singular Value Decomposition (SVD) are discussed. Traditional algorithms using hardware division and square root are replaced with the special purpose CORDIC algorithms for computing vector rotations and inverse tangents. The CORDIC 2 x 2 SVD processor can be twice as fast as one assembled from traditional hardware units. A prototype VLSI implementation of a CORDIC SVD processor array is planned for use in real-time signal processing applications.en_US
dc.description.sponsorshipArmy Research Officeen_US
dc.description.sponsorshipCornell Program on Submicrometer Structuresen_US
dc.identifier.citationJ. R. Cavallaro and F. T. Luk, "CORDIC Arithmetic for an SVD Processor," 1987.en_US
dc.identifier.doihttp://dx.doi.org/10.1109/ARITH.1987.6158686en_US
dc.identifier.otherhttp://scholar.google.com/scholar?cluster=2454426890384439275&hl=en&as_sdt=0,44en_US
dc.identifier.urihttps://hdl.handle.net/1911/64179en_US
dc.language.isoengen_US
dc.publisherThe Computer Society of the IEEEen_US
dc.subjectSingular Value Decomposition (SVD)en_US
dc.subjectCORDICen_US
dc.subjectVLSIen_US
dc.titleCORDIC Arithmetic for an SVD Processoren_US
dc.typeConference paperen_US
dc.type.dcmiTexten_US
dc.type.dcmiTexten_US
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