High-Throughput Contention-Free Concurrent Interleaver Architecture for Multi-Standard Turbo Decoder

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dc.citation.conferenceDate2011en_US
dc.citation.conferenceNameIEEE International Conference on Application-specific System, Architectures and Processors (ASAP)en_US
dc.citation.firstpage113
dc.citation.lastpage121
dc.citation.locationSanta Monica, CAen_US
dc.contributor.authorWang, Guohui
dc.contributor.authorSun, Yang
dc.contributor.authorCavallaro, Joseph R.
dc.contributor.authorGuo, Yuanbin
dc.contributor.orgCenter for Multimedia Communicationen_US
dc.date.accessioned2012-06-28T16:09:26Z
dc.date.available2012-06-28T16:09:26Z
dc.date.issued2011-09-01eng
dc.description.abstractTo meet the higher data rate requirement of emerging wireless communication technology, numerous parallel turbo decoder architectures have been developed. However, the interleaver has become a major bottleneck that limits the achievable throughput in the parallel decoders due to the massive memory conflicts. In this paper, we propose a flexible Double-Buffer based Contention-Free (DBCF) interleaver architecture that can efficiently solve the memory conflict problem for parallel turbo decoders with very high parallelism. The proposed DBCF architecture enables high throughput concurrent interleaving for multi-standard turbo decoders that support UMTS/HSPA+, LTE and WiMAX, with small datapath delays and low hardware cost. We implemented the DBCF interleaver with a 65nm CMOS technology. The implementation of this highly efficient DBCF interleaver architecture shows significant improvement in terms of the maximum throughput and occupied chip area compared to the previous work.en_US
dc.description.sponsorshipHuaweien_US
dc.description.sponsorshipNational Science Foundationen_US
dc.identifier.citationG. Wang, Y. Sun, J. R. Cavallaro and Y. Guo, "High-Throughput Contention-Free Concurrent Interleaver Architecture for Multi-Standard Turbo Decoder," 2011.*
dc.identifier.doihttp://dx.doi.org/10.1109/ASAP.2011.6043259en_US
dc.identifier.otherhttp://scholar.google.com/scholar?cluster=6777021284623106221&hl=en&as_sdt=0,44
dc.identifier.urihttps://hdl.handle.net/1911/64349
dc.language.isoengen
dc.publisherIEEEen_US
dc.subjectParallel turbo decoderen_US
dc.subjectInterleaveren_US
dc.subjectContention-freeen_US
dc.subjectUMTSen_US
dc.subjectHSPA+en_US
dc.subjectLTEen_US
dc.subjectWiMAXen_US
dc.subjectMulti-standarden_US
dc.titleHigh-Throughput Contention-Free Concurrent Interleaver Architecture for Multi-Standard Turbo Decoderen_US
dc.typeConference paperen_US
dc.type.dcmiTexten
dc.type.dcmiTexten_US
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