Low Complexity System-On-Chip Architectures Of Optimal Parallel-Residue-Compensation In CDMA Systems

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dc.citation.bibtexNameinproceedingsen_US
dc.citation.conferenceNameIEEE International Symposium on Circuits and Systems (ISCAS)en_US
dc.citation.firstpage77en_US
dc.citation.issueNumber4en_US
dc.citation.lastpage80en_US
dc.citation.volumeNumber4en_US
dc.contributor.authorGuo, Yuanbinen_US
dc.contributor.authorMcCain, Dennisen_US
dc.contributor.authorCavallaro, Joseph R.en_US
dc.contributor.orgCenter for Multimedia Communications (http://cmc.rice.edu/)en_US
dc.date.accessioned2007-10-31T00:45:50Zen_US
dc.date.available2007-10-31T00:45:50Zen_US
dc.date.issued2004-05-01en_US
dc.date.modified2006-02-06en_US
dc.date.note2003-12-20en_US
dc.date.submitted2004-05-01en_US
dc.descriptionConference Paperen_US
dc.description.abstractIn this paper, we propose a novel multi-stage Parallel-Residue-Compensation (PRC) receiver architecture for enhanced suppression of the MAI in CDMA systems. We extract the commonality to avoid the direct Interference Cancellation and reduce the algorithm complexity from O(K²N) to O(KN). In the second part, scalable VLSI architectures are implemented in a FPGA prototyping system with an efficient Precision-C System-on-Chip (SOC) design methodology. Hardware efficiency is achieved by investigating multi-level parallelism and pipelines. The design of Sum-Sub-MUX Unit (SMU) combinational logic avoids the usage of dedicated multipliers with at least 10X saving in hardware resources. The most area/timing efficient design only uses area similar to the most area constraint architecture but gives at least 4X speedup over a conventional design.en_US
dc.description.sponsorshipNational Science Foundationen_US
dc.description.sponsorshipNational Science Foundationen_US
dc.description.sponsorshipNational Science Foundationen_US
dc.identifier.citationY. Guo, D. McCain and J. R. Cavallaro, "Low Complexity System-On-Chip Architectures Of Optimal Parallel-Residue-Compensation In CDMA Systems," vol. 4, no. 4, 2004.en_US
dc.identifier.urihttps://hdl.handle.net/1911/19926en_US
dc.language.isoengen_US
dc.subjectSystem-On-Chipen_US
dc.subjectParallel-Residue-Compensationen_US
dc.subjectInterference Cancellationen_US
dc.subjectCDMAen_US
dc.subject.keywordSystem-On-Chipen_US
dc.subject.keywordParallel-Residue-Compensationen_US
dc.subject.keywordInterference Cancellationen_US
dc.subject.keywordCDMAen_US
dc.titleLow Complexity System-On-Chip Architectures Of Optimal Parallel-Residue-Compensation In CDMA Systemsen_US
dc.typeConference paperen_US
dc.type.dcmiTexten_US
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