A LOW-POWER 1-Gbps RECONFIGURABLE LDPC DECODER DESIGN FOR MULTIPLE 4G WIRELESS STANDARDS
| dc.citation.conferenceDate | 2008 | en_US |
| dc.citation.conferenceName | IEEE International System-on-Chip (SOC) Conference | en_US |
| dc.citation.firstpage | 367 | |
| dc.citation.lastpage | 370 | |
| dc.citation.location | Newport Beach, CA | en_US |
| dc.contributor.author | Sun, Yang | |
| dc.contributor.author | Cavallaro, Joseph R. | |
| dc.contributor.org | Center for Multimedia Communication | en_US |
| dc.date.accessioned | 2012-06-13T21:33:21Z | |
| dc.date.available | 2012-06-13T21:33:21Z | |
| dc.date.issued | 2008-09-01 | eng |
| dc.description.abstract | In this paper we present an efficient system-on-chip implementation of a 1-Gbps LDPC decoder for 4G (or beyond 3G) wireless standards. The decoder has a scalable data path and can be dynamically reconfigured to support multiple 4G standards. We utilize a pipelined version of the layered belief propagation algorithm to achieve partial-parallel decoding of structured LDPC codes. Instead of using the sub-optimal Minsum algorithm, we propose to use the powerful belief propagation (BP) decoding algorithm by designing an area-efficient soft-input soft-output (SISO) decoder. Two power saving schemes are employed to reduce the power consumption up to 65%. The decoder has been synthesized, placed, and routed on a TSMC 90nm 1.0V 8-metal layer CMOS technology with a total area of 3.5 mm2. The maximum clock frequency is 450 MHz and the estimated peak power consumption is 410 mW. | en_US |
| dc.description.sponsorship | Nokia | en_US |
| dc.description.sponsorship | National Science Foundation | en_US |
| dc.identifier.citation | Y. Sun and J. R. Cavallaro, "A LOW-POWER 1-Gbps RECONFIGURABLE LDPC DECODER DESIGN FOR MULTIPLE 4G WIRELESS STANDARDS," 2008. | * |
| dc.identifier.doi | http://dx.doi.org/10.1109/SOCC.2008.4641546 | en_US |
| dc.identifier.other | http://scholar.google.com/scholar?cluster=17679370312231082906&hl=en&as_sdt=0,44 | |
| dc.identifier.uri | https://hdl.handle.net/1911/64263 | |
| dc.language.iso | eng | en |
| dc.publisher | IEEE | en_US |
| dc.subject | LDPC decoder | en_US |
| dc.subject | Wireless systems | en_US |
| dc.subject | CMOS | en_US |
| dc.subject | Pipelined | en_US |
| dc.subject | SISO decoder | en_US |
| dc.subject.other | Best Paper Award | en_US |
| dc.title | A LOW-POWER 1-Gbps RECONFIGURABLE LDPC DECODER DESIGN FOR MULTIPLE 4G WIRELESS STANDARDS | en_US |
| dc.type | Conference paper | en_US |
| dc.type.dcmi | Text | en |
| dc.type.dcmi | Text | en_US |