The impact of instruction-level parallelism on multiprocessor performance and simulation methodology

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dc.contributor.advisorAdve, Sarita V.
dc.creatorPai, Vijay Sadananda
dc.date.accessioned2009-06-04T08:18:20Z
dc.date.available2009-06-04T08:18:20Z
dc.date.issued1997
dc.description.abstractCurrent microprocessors exploit high levels of instruction-level parallelism (ILP). This thesis presents the first detailed analysis of the impact of such processors on shared-memory multiprocessors. We find that ILP techniques substantially reduce CPU time in multiprocessors, but are less effective in reducing memory stall time for our applications. Consequently, despite the latency-tolerating techniques incorporated in ILP processors, memory stall time becomes a larger component of execution time and parallel efficiencies are generally poorer in our ILP-based multiprocessor than in an otherwise equivalent previous-generation multiprocessor. We identify clustering independent read misses together in the processor instruction window as a key optimization to exploit the ILP features of current processors. We also use the above analysis to examine the validity of direct-execution simulators with previous-generation processor models to approximate ILP-based multiprocessors. We find that, with appropriate approximations, such simulators can reasonably characterize the behavior of applications with poor overlap of read misses. However, they can be highly inaccurate for applications with high overlap of read misses.
dc.format.extent57 p.en_US
dc.format.mimetypeapplication/pdf
dc.identifier.callnoTHESIS E.E. 1997 PAI
dc.identifier.citationPai, Vijay Sadananda. "The impact of instruction-level parallelism on multiprocessor performance and simulation methodology." (1997) Master’s Thesis, Rice University. <a href="https://hdl.handle.net/1911/17116">https://hdl.handle.net/1911/17116</a>.
dc.identifier.urihttps://hdl.handle.net/1911/17116
dc.language.isoeng
dc.rightsCopyright is held by the author, unless otherwise indicated. Permission to reuse, publish, or reproduce the work beyond the bounds of fair use or other exemptions to copyright law must be obtained from the copyright holder.
dc.subjectElectronics
dc.subjectElectrical engineering
dc.subjectComputer science
dc.titleThe impact of instruction-level parallelism on multiprocessor performance and simulation methodology
dc.typeThesis
dc.type.materialText
thesis.degree.departmentElectrical Engineering
thesis.degree.disciplineEngineering
thesis.degree.grantorRice University
thesis.degree.levelMasters
thesis.degree.nameMaster of Science
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