The impact of instruction-level parallelism on multiprocessor performance and simulation methodology

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dc.contributor.advisorAdve, Sarita V.en_US
dc.creatorPai, Vijay Sadanandaen_US
dc.date.accessioned2009-06-04T08:18:20Zen_US
dc.date.available2009-06-04T08:18:20Zen_US
dc.date.issued1997en_US
dc.description.abstractCurrent microprocessors exploit high levels of instruction-level parallelism (ILP). This thesis presents the first detailed analysis of the impact of such processors on shared-memory multiprocessors. We find that ILP techniques substantially reduce CPU time in multiprocessors, but are less effective in reducing memory stall time for our applications. Consequently, despite the latency-tolerating techniques incorporated in ILP processors, memory stall time becomes a larger component of execution time and parallel efficiencies are generally poorer in our ILP-based multiprocessor than in an otherwise equivalent previous-generation multiprocessor. We identify clustering independent read misses together in the processor instruction window as a key optimization to exploit the ILP features of current processors. We also use the above analysis to examine the validity of direct-execution simulators with previous-generation processor models to approximate ILP-based multiprocessors. We find that, with appropriate approximations, such simulators can reasonably characterize the behavior of applications with poor overlap of read misses. However, they can be highly inaccurate for applications with high overlap of read misses.en_US
dc.format.extent57 p.en_US
dc.format.mimetypeapplication/pdfen_US
dc.identifier.callnoTHESIS E.E. 1997 PAIen_US
dc.identifier.citationPai, Vijay Sadananda. "The impact of instruction-level parallelism on multiprocessor performance and simulation methodology." (1997) Master’s Thesis, Rice University. <a href="https://hdl.handle.net/1911/17116">https://hdl.handle.net/1911/17116</a>.en_US
dc.identifier.urihttps://hdl.handle.net/1911/17116en_US
dc.language.isoengen_US
dc.rightsCopyright is held by the author, unless otherwise indicated. Permission to reuse, publish, or reproduce the work beyond the bounds of fair use or other exemptions to copyright law must be obtained from the copyright holder.en_US
dc.subjectElectronicsen_US
dc.subjectElectrical engineeringen_US
dc.subjectComputer scienceen_US
dc.titleThe impact of instruction-level parallelism on multiprocessor performance and simulation methodologyen_US
dc.typeThesisen_US
dc.type.materialTexten_US
thesis.degree.departmentElectrical Engineeringen_US
thesis.degree.disciplineEngineeringen_US
thesis.degree.grantorRice Universityen_US
thesis.degree.levelMastersen_US
thesis.degree.nameMaster of Scienceen_US
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