An FPGA-based Daughtercard for TIs C6000 family of DSKs
dc.citation.bibtexName | inproceedings | en_US |
dc.citation.conferenceName | International Conference on Microelectronic Systems Education (MSE) | en_US |
dc.citation.firstpage | 85 | en_US |
dc.citation.lastpage | 86 | en_US |
dc.citation.location | Anaheim, CA | en_US |
dc.contributor.author | Gadhiok, Manik | en_US |
dc.contributor.author | Hardy, Ricky | en_US |
dc.contributor.author | Murphy, Patrick | en_US |
dc.contributor.author | Frantz, Patrick | en_US |
dc.contributor.author | Choi, Hyeokho | en_US |
dc.contributor.author | Cavallaro, Joseph R. | en_US |
dc.contributor.org | Digital Signal Processing (http://dsp.rice.edu/) | en_US |
dc.date.accessioned | 2007-10-31T00:44:19Z | en_US |
dc.date.available | 2007-10-31T00:44:19Z | en_US |
dc.date.issued | 2005-06-01 | en_US |
dc.date.modified | 2005-11-14 | en_US |
dc.date.note | 2005-01-31 | en_US |
dc.date.submitted | 2005-06-01 | en_US |
dc.description | Conference Paper | en_US |
dc.description.abstract | In this paper we present an FPGA-based daughtercard designed for TIs C6000 family of DSP Starter Kits (DSKs). The hardware, initially designed for a course project, provides a platform for studying heterogeneous systems and hardware software co-design. Students will leverage the DSK-FPGA system for rapid prototyping of signal processing algorithms and to study task-partitioning and system integration. These techniques are becoming increasingly important for system designers as we move to system-on-chip (SOC) devices. The daughtercard hardware is fully functional, and a software package is being developed to provide a seamless communication interface between the DSK and FPGA. | en_US |
dc.description.sponsorship | National Science Foundation | en_US |
dc.identifier.citation | M. Gadhiok, R. Hardy, P. Murphy, P. Frantz, H. Choi and J. R. Cavallaro, "An FPGA-based Daughtercard for TIs C6000 family of DSKs," 2005. | en_US |
dc.identifier.doi | http://dx.doi.org/10.1109/MSE.2005.19 | en_US |
dc.identifier.uri | https://hdl.handle.net/1911/19892 | en_US |
dc.language.iso | eng | en_US |
dc.relation.project | http://www.ece.rice.edu/~gadhiok/elec434/project | en_US |
dc.relation.software | http://www.ece.rice.edu/~gadhiok/elec434/project | en_US |
dc.subject | novel curricula | en_US |
dc.subject | rapid prototyping | en_US |
dc.subject | task-partitioning | en_US |
dc.subject | system-on-a-chip | en_US |
dc.subject | FPGA | en_US |
dc.subject | signal processing | en_US |
dc.subject.keyword | novel curricula | en_US |
dc.subject.keyword | rapid prototyping | en_US |
dc.subject.keyword | task-partitioning | en_US |
dc.subject.keyword | system-on-a-chip | en_US |
dc.subject.keyword | FPGA | en_US |
dc.subject.keyword | signal processing | en_US |
dc.subject.other | Education | en_US |
dc.title | An FPGA-based Daughtercard for TIs C6000 family of DSKs | en_US |
dc.type | Conference paper | en_US |
dc.type.dcmi | Text | en_US |
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