Electrical and Computer Engineering

Permanent URI for this community

https://hdl.handle.net/1911/8315

Browse

Browsing Electrical and Computer Engineering by Subject "3GPP LTE"

Now showing 1 - 4 of 4
  • Thumbnail Image
    Item
    Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder
    (Elsevier, 2011-09-01) Sun, Yang; Cavallaro, Joseph R.; Center for Multimedia Communication
    We present an efficient VLSI architecture for 3GPP LTE/LTE-Advance Turbo decoder by utilizing the algebraic-geometric properties of the quadratic permutation polynomial (QPP) interleaver. The high throughput 3GPP LTE/LTE-Advance Turbo codes require a highly-parallel decoder architecture. Turbo interleaver is known to be the main obstacle to the decoder parallelism due to the collisions it introduces in accesses to memory. The QPP interleaver solves the memory contention issues when several MAP decoders are used in parallel to improve Turbo decoding throughput. In this paper, we propose a low-complexity QPP interleaving address generator and a multi-bank memory architecture to enable parallel Turbo decoding. Design trade-offs in terms of area and throughput efficiency are placed an routed in a 65-nm CMOS technology with a core area of 8.3mm2 and a maximum clock frequency of 400 MHz. This parallel decoder, comprising 64 MAP decoder cores, can achieve a maximum decoding throughput of 1.28 Gbps at 6 iterations.
  • Thumbnail Image
    Item
    FPGA Prototyping of A High Data Rate LTE Uplink Baseband Receiver
    (IEEE, 2009-11-01) Wang, Guohui; Yin, Bei; Amiri, Kiarash; Sun, Yang; Wu, Michael; Cavallaro, Joseph R.; Center for Multimedia Communication
    The Third Generation Partnership Project (3GPP) Long Term Evolution (LTE) standard is becoming the appropriate choice to pave the way for the next generation wireless and cellular standards. While the popular OFDM technique has been adopted and implemented in previous standards and also in the LTE downlink, it suffers from high peak-to-average-power ratio (PAPR). High PAPR requires more sophisticated power amplifiers (PAs) in the handsets and would result in lower efficiency PAs. In order to combat such effects, the LTE uplink choice of transmission is the novel Single Carrier Frequency Division Multiple Access (SC-FDMA) scheme which has lower PAPR due to its inherent signal structure. While reducing the PAPR, the SC-FDMA requires a more complicated detector structure in the base station for multi-antenna and multi-user scenarios. Since the multi-antenna and multi-user scenarios are critical parts of the LTE standard to deliver high performance and data rate, it is important to design novel architectures to ensure high reliability and data rate in the receiver. In this paper, we propose a flexible architecture of a high data rate LTE uplink receiver with multiple receive antennas and implemented a single FPGA prototype of this architecture. The architecture is verified on the WARPLab (a software defined radio platform based on Rice Wireless Open-access Research Platform) and tested in the real over-the-air indoor channel.
  • Thumbnail Image
    Item
    Implementation of a 3GPP LTE Turbo Decoder Accelerator on GPU
    (IEEE, 2010-10-01) Wu, Michael; Cavallaro, Joseph R.; Center for Multimedia Communication
    This paper presents a 3GPP LTE compliant turbo decoder accelerator on GPU. The challenge of implementing a turbo decoder is finding an efficient mapping of the decoder algorithm on GPU, e.g. finding a good way to parallelize workload across cores and allocate and use fast on-die memory to improve throughput. In our implementation, we increase throughput through 1) distributing the decoding workload for a codeword across multiple cores, 2) decoding multiple codewords simultaneously to increase concurrency and 3) employing memory optimization techniques to reduce memory bandwidth requirements. In addition, we analyze how different MAP algorithm approximations affect both throughput and bit error rate (BER) performance of this decoder.
  • Thumbnail Image
    Item
    Implementation of LS, MMSE and SAGE Channel Estimators for Mobile MIMO-OFDM
    (IEEE, 2012-12-01) Ketonen, Johanna; Juntti, Markku; Ylioinas, Jari; Cavallaro, Joseph R.; CMC
    The use of decision directed (DD) channel estimation in a multiple-input multiple-output (MIMO) orthogonal frequency division multiplexing (OFDM) downlink receiver is studied in this paper. The 3GPP long term evolution (LTE) based pilot structure is used as a benchmark. The space-alternating generalized expectation-maximization (SAGE) algorithm is used to improve the performance from that of the pilot symbol based least-squares (LS) channel estimator. The DD channel estimation improves the performance with high user velocities, where the pilot symbol density is not sufficient. Minimum mean square error (MMSE) filtering can also be used in estimating the channel in between pilot symbols. The DD channel estimation can be used to reduce the pilot overhead without any performance degradation by transmitting data instead of pilot symbols. The pilot overhead is reduced to a third of the LTE pilot overhead, obtaining a ten percent increase in throughput. The pilot based LS, MMSE and the SAGE channel estimators are implemented and the performance-complexity trade-offs are studied.