Browsing by Author "Vaya, Mani"

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    Handset Detector Architectures for DS-CDMA Wireless Systems
    (2002-05-20) Livingston, Frank; Chandrasekhar, Vikram; Vaya, Mani; Cavallaro, Joseph R.; Center for Multimedia Communications (http://cmc.rice.edu/)
    This paper investigates detector architectures for wireless handsets employing DS-CDMA. The code-matched filter (MF) and minimum output energy (MOE) detectors are analyzed with respect to fixed-point arithmetic behavior. Architectures employing fixed-point arithmetic are then proposed for these detectors. The maximum throughput of these architectures and the associated costs in terms of area usage and power consumption are evaluated. Results of the fixed-point analysis indicate that the MOE detector is more susceptible to quantization than the MF detector. Results of implementation indicate that the superior performance of the MOE detector is achieved at a considerably higher cost in terms of area usage and power consumption. Finally, comparison of hardware implementation with software-based DSP implementation indicates that software approaches result in considerably lower throughputs.
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    VITURBO: A Reconfigurable Architecture for Ubiquitous Wireless Networks
    (2002-08-01) Vaya, Mani; Center for Multimedia Communications (http://cmc.rice.edu/)
    A run-time reconfigurable architecture for ubiquitous wireless networks has been designed and implemented. Reconfigurable architectures have the ability to change themselves dynamically thus presenting a viable proposition for handset design for ubiquitous networks, where a key requirement is the flexibility to switch across different standards in different environments, examples of which are Orthogonal Frequency Division Multiplexing based IEEE 802.11a Wireless Local Area Networks (WLAN) and Code Division Multiple Access based 3rd Generation (3G) cellular networks. Channel encoding and decoding are essential components of these communication systems and different forms of convolutional encoders and decoders are used. We present the design and implementation of a novel reconfigurable architecture that can decode a range of convolutionally coded data (constraint lengths 3-9); and Turbo coded data (constraint length 4). Our architecture can support channel decoding for most of the current communication systems like WLAN, 3G, and Global System for Mobile Communications.
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    VITURBO: A Reconfigurable Architecture for Viterbi and Turbo Decoding
    (2003-04-20) Cavallaro, Joseph R.; Vaya, Mani; Center for Multimedia Communications (http://cmc.rice.edu/)
    A runtime reconfigurable architecture for high speed Viterbi and Turbo decoding is designed and implemented on an FPGA. The architecture can be reconfigured to decode a range of convolutionally coded data with constraint lengths varying from 3 to 9, rates 1/2 and 1/3, and various generator polynomials. It can also be reconfigured to decode Turbo coded data with constraint length 4 and rate 1/3. Reconfiguration of the architecture requires a single clock cycle and does not require FPGA reprogramming. The proposed architecture can deliver data rates up to 60.5 Mbps for Viterbi decoding and 3.54 Mbps for Turbo decoding, making it suitable for a range of wireless communication standards like IEEE 802.11a, 3GPP, GSM, GPRS, and many others.