Browsing by Author "Peng, Yuhan"

Now showing 1 - 3 of 3
  • Thumbnail Image
    Item
    Enabling QoS Controls in Modern Distributed Storage Platforms
    (2020-10-08) Peng, Yuhan; Varman, Peter
    Distributed storage systems provide a scalable approach for hosting multiple clients on a consolidated storage platform. The use of shared infrastructure can lower costs but exacerbates the problem of fairly allocating the IO resources. Providing performance Quality-of-Service (QoS) guarantees in a distributed storage environment poses unique challenges. Workload demands of clients shift unpredictably between servers as their locality and IO intensities fluctuate. This complicates the problem of providing QoS controls like reservations and limits that are based on aggregate client service, as well as providing differentiated tail latency guarantees to the clients. In this thesis, we present novel approaches for providing bandwidth allocation and response time QoS in distributed storage platforms. For bandwidth allocation QoS, we develop a token-based scheduling framework to guarantee the maximum and minimum aggregate throughput of different clients. We introduce a novel algorithm called pTrans for solving the token allocation problem. pTrans is provably optimal and has better theoretical and empirical scalability than competing approaches based on linear-programming or max-flow formulations. For the response time QoS, we introduce Fair-EDF, a framework that extends the earliest deadline first (EDF) scheduler to provide fairness control while supporting latency guarantees.
  • Thumbnail Image
    Item
    Method for assuring quality of service in distributed storage system, control node, and system
    (2022-05-03) Yu, Si; Gong, Junhui; Varman, Peter; Peng, Yuhan; Rice University; Huawei Technologies Co., Ltd.; William Marsh Rice University; United States Patent and Trademark Office
    The present disclosure discloses a method for assuring quality of service in a storage system, where a control node calculates, based on a quantity of remaining I/O requests of a target storage node in a unit time, a quantity of I/O requests required by a storage resource to reach a lower assurance limit in the unit time, and a quantity of I/O requests need to be processed by the target storage node for the storage resource in the unit time, a lower limit quantity of I/O requests that can be processed by the target storage node for the storage resource in the unit time; allocates, based on the lower limit quantity of I/O requests, a lower limit quantity of tokens of the storage resource on the target storage node in the unit time to the storage resource; and sends the lower limit quantity of tokens to the target storage node.
  • Thumbnail Image
    Item
    Static Cost Estimation for Data Layout Selection on GPUs
    (2017-09-11) Peng, Yuhan; Sarkar, Vivek
    Performance modeling provides mathematical models and quantitative analysis for designing and optimizing computer systems and architectures. For many data-intensive applications, high-latency memory accesses often dominate execution time. Thus, performance modeling for memory accesses on high performance architectures has become an important research topic. The data layout of an application refers to the way in which data is stored and organized. In high performance computation, the data layout can significantly affect the efficiency of memory access operations. In recent years, the problem of data layout selection has been well studied on various multi-core CPU and some heterogeneous architectures. GPUs have memory hierarchies different from multi-core CPUs. While data layout selection on GPUs has been studied previously, none of the prior work provides a mathematical cost model for data layout selection on GPUs. This motivates us to investigate static cost analysis methods to guide data layout selection work, and perhaps even the design of new SIMT architectures. This thesis presents a comprehensive cost analysis for data layout selection on GPUs. We build our cost function based on knowledge of the GPU memory hierarchy, and develop an algorithm which enables researchers to perform compile time cost estimation for a given data layout. Furthermore, we introduce a new vector based cost representation of the estimated cost, which can better estimate the memory access cost of applications with dynamic length loops. We apply our cost analysis to benchmarks considered by prior work on data layout selection, and our experimental results show that our cost analysis can accurately predict the relative costs of different data layouts.