Browsing by Author "Lou, Feifei"

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    An FPGA Based Rapid Prototyping Platform for MIMO Systems
    (2003-11-20) Murphy, Patrick; Lou, Feifei; Sabharwal, Ashutosh; Frantz, Patrick; Center for Multimedia Communications (http://cmc.rice.edu/)
    There exists a seemingly limitless demand for wireless communications systems capable of higher datarates with lower power consumption. While the demand for improvement in these systems seems limitless, the spectrum allocated for providing such services is undeniably restricted. There is a great deal of research directed at solving the problem of providing more wireless communications capabilities without any increase in allocated spectrum. One significant result of this research has been the development of algorithms targeted at transmitters and receivers equipped with multiple antennas, often described as multiple-input multiple-output (MIMO) systems. We describe in this paper a FPGA-based platform designed to explore MIMO algorithms and architectures in real hardware. This system utilizes Xilinx?s System Generator for DSP, a Simulink blockset designed to allow both PC-based simulation and FPGA implementation of DSP designs. MIMO algorithms implemented in System Generator are targeted to FPGA systems connected to 2.4 GHz spread spectrum radios. These radios are interconnected via a pair of Spirent RF channel emulators and can realize a variety of transmitter and receiver configurations. The use of FPGAs as baseband processors allows a great deal of flexibility in implementing designs while maintaining the capability to measure the resource utilization and power consumption of real hardware. Such measurements play a crucial role in evaluating the suitability of algorithms for deployment in real-world systems.
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    A FPGA­Based Experimental PHY for 802.11b WLAN
    (2003-10-20) Lou, Feifei; Murphy, Patrick; Frantz, Patrick; Center for Multimedia Communications (http://cmc.rice.edu/)
    The swift proliferation of wireless data communication systems, and the ever-increasing demand for faster data rates requires that engineers be able to quickly design, implement and test new wireless algorithms for data communications. While simulation is useful, it is often beneficial to verify these algorithms in real hardware. This process of implementation can provide useful feedback to the algorithm designer (e.g. the hardware resources used by an algorithm). This paper provides a description of a rapid prototyping system used to design, implement, and validate an 802.11b PHY as a starting point for developing new wireless data algorithms.
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    A Hardware Testbed for the Implementation and Evaluation of MIMO Algorithms
    (2003-10-20) Murphy, Patrick; Lou, Feifei; Frantz, Patrick; Center for Multimedia Communications (http://cmc.rice.edu/)
    As the demand for higher performance wireless communications continues to grow, novel algorithms have been developed which provide increased performance and efficiency. One such class of algorithms involves the use of multiple antennas on either end of a wireless link. Many of these multiple input, multiple output (MIMO) algorithms offer impressive performance gains over their single antenna counterparts. The practicality of implementing such algorithms in a real system, however, is a topic in need of further exploration. We present in this paper a testbed designed specifically to test such algorithms. This testbed provides hardware for baseband processing, up and downconversion to RF and emulation of multiple wireless channels. It was designed to provide sufficient exibility to implement a wide range of algorithms while preserving the ability to evaluate an algorithm's resource and power requirements. The testbed hardware and configuration options are presented, along with a basic demonstration of its functionality.
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    Transceiver Design for Efficient Channel Estimation in MIMO OFDM Systems
    (2005-12-01) Lou, Feifei; Center for Multimedia Communications (http://cmc.rice.edu/)
    In this thesis, we first compare the least squares (LS) channel estimation performance in terms of mean squared error (MSE) with the perfect knowledge of channel length $L$ versus the estimation without the knowledge of $L$. This comparison motivates us to estimate the channel in two steps by exploiting the instantaneous delay spread. We show that the channel estimation performance can be improved by $5$ dB even in the presence of channel mismatch. Then we propose the optimal training sequence which achieves not only the minimum MSE of LS channel estimation, but also the minimum peak-to-average power ratio (PAPR) at transmitter with a low computational complexity. Finally we describe all the necessary synchronization functions and FPGA implementation in the SISO OFDM receiver. And this receiver serves as the foundation to build up a wireless testbed to verify the new algorithms.
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    Transceiver design for efficient channel estimation in MIMO OFDM systems
    (2006) Lou, Feifei; Sabharwal, Ashutosh
    In this thesis, we first compare the least squares (LS) channel estimation performance in terms of mean squared error (MSE) with the perfect knowledge of channel length L versus the estimation without the knowledge of L. This comparison motivates us to estimate the channel in two steps by exploiting the instantaneous delay spread. We show that the channel estimation performance can be improved by 5 dB even in the presence of channel mismatch. Then we propose the optimal training sequence which achieves not only the minimum MSE of LS channel estimation, but also the minimum peak-to-average power ratio (PAPR) at transmitter with a low computational complexity. Finally we describe all the necessary synchronization functions and FPGA implementation in the SISO OFDM receiver. And this receiver serves as the foundation to build up a wireless testbed to verify the new algorithms.