Browsing by Author "Liu, Qingyue"

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    Ouroboros Wear-leveling: A Two-level Hierarchical Wear-leveling Model for NVRAM
    (2017-03-28) Liu, Qingyue; Varman, Peter J.
    Emerging non-volatile memory (NVM) technologies have a limit on the number of writes that can be made to any cell, similar to the erasure limits in NAND Flash. This motivates the need for wear-leveling techniques to distribute the writes evenly among the cells. Unlike NAND Flash, cells in NVM can be rewritten without the need for erasing the entire containing block, avoiding the issues of space reclamation and garbage collection, motivating alternate approaches to the problem. In this thesis, we propose a hierarchical wear-leveling model called Ouroboros Wear-leveling. Ouroboros uses a two-level strategy whereby frequent low-cost intra-region wear-leveling at small granularity is combined with inter-region wear-leveling at a larger time interval and granularity. Ouroboros constructs the optimal lexicographically smooth block permutation based on the current wear and access distributions. The past access patterns are used to predict the accesses till the next inter-region wear leveling. Two optimizations, adaptive pruning and randomization, are applied to the cycle decomposition of the permutation in order to reduce the number of block movements and avoid destructive repetitive patterns that accelerate wear out. We also propose a way to optimize wear-leveling parameter settings with target smoothness level under limited timing and space overhead constraints for different memory architectures and trace characteristics. Several experiments are performed on both synthetically-generated memory traces with special characteristics and two block-level storage traces generated by Microsoft and FIU. The results show that Ouroboros Wear-leveling can distribute writes smoothly across the whole NVM with around 0.2% space overhead and around 0.52% timing overhead for a 512GB memory with 500MB/s write rate.
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    Rethinking Storage System Design in Distributed NVRAM+RDMA Clusters
    (2020-12-03) Liu, Qingyue; Varman, Peter J.
    Recent advances in hardware technologies raise new opportunities for architecting storage systems to exploit emerging NVRAM memory devices, fast remote-memory RDMA networking, and large numbers of processor cores. These technologies provide new opportunities for creating scalable high-throughput data management systems with low latency and strong consistency guarantees. In this thesis, we investigate the design space for distributed storage systems based on these emerging technologies. The design focuses on three components: a novel high-performance and strongly consistent data access protocol, new communication abstractions, and QoS controls. We present Telepathy, a novel data access protocol for distributed key-value storage systems. Telepathy supports replicated data storage for fault tolerance and guarantees strong consistency while supporting high-volume concurrent read/write access. Our read protocol can perform (largely) silent consistent reads from any of the replica nodes holding an object, while our write protocol exploits remote atomics and non-volatile buffers to silently resolve write contention. For inter-server communication, we present a new distributed communication channel (DCC) that separates control and data communication directly at the RNIC. By using different RDMA semantics, our scheme avoids frequent remote processor interruption, and improves latency, throughput, CPU utilization, and memory usage. For QoS control, we design a new algorithm to support QoS for applications using one-sided data access operations. A silent token dispatch mechanism is designed to inform storage nodes of the real-time throughput of connected clients, and adaptively change the token distribution to guarantee clients meet their target reservations with small overhead. Our experiments on an RDMA-enabled cluster using YCSB benchmarks show that our distributed key-value store can achieve microsecond-range reads and writes with small tail latencies, GBps-range data access bandwidth, low CPU utilization, and strong data consistency guarantees. The system also supports QoS reservations with only minor performance impact.