Browsing by Author "Lingamneni, Avinash"
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Item Computing device using inexact computing architecture processor(2013-11-19) Palem, Krishna V.; Chakrapani, Lakshmi Narasimhan; Lingamneni, Avinash; Rice University; United States Patent and Trademark OfficeIn general, in one aspect, the invention relates to a computer readable medium including software instructions which, when executed by a processor, perform a method, the method including receiving a first method call from an application, wherein the first method call is associated with a first application component; obtaining a first application component error tolerance (ACET) value associated with the first method call; determining, using the first ACET value and a first inexact amount value (IAV) of a first inexact computing architecture (ICA) processor, that the first ICA processor is available to execute the first method call; and processing the first method call using the first ICA processor.Item Implementing Energy Parsimonious Circuits through Inexact Designs(2011) Lingamneni, Avinash; Palem, Krishna V.Inexact Circuits or circuits in which accuracy of the output can be traded for cost (energy, delay and/or area) savings, have been receiving increasing attention of late due to invariable inaccuracies in nanometer-scale circuits and a concomitant growing desire for ultra low energy embedded systems. Most of the previous approaches to realize inexact circuits relied on scaling of circuit-level operational parameters (such as supply voltage) to achieve the cost and accuracy tradeoffs, and suffered from serious drawbacks of significant implementation overheads that drastically reduced the gains. In this thesis, two novel architecture-level approaches called Probabilisttc Pruning and Probabilistic Logic Minimization are proposed to realize inexact circuits with zero overhead. Extensive simulations on various architectures of datapath elements and a prototype chip fabrication demonstrate that normalized gains as large as 2X-9.5X in Energy-Delay-Area product can be obtained for relative error as low as 10 -6 % - 1% compared to corresponding conventional correct designs.Item Innovation for Sustainability in Information and Communication TechnologiesBronk, Christopher; Lingamneni, Avinash; Palem, Krishna; James A. Baker III Institute for Public PolicyItem On the use of inexact, pruned hardware in atmospheric modelling(Royal Society, 2014) Düben, Peter D.; Joven, Jaume; Lingamneni, Avinash; McNamara, Hugh; De Micheli, Giovanni; Palem, Krishna V.; Palmer, T.N.Inexact hardware design, which advocates trading the accuracy of computations in exchange for significant savings in area, power and/or performance of computing hardware, has received increasing prominence in several error-tolerant application domains, particularly those involving perceptual or statistical end-users. In this paper, we evaluate inexact hardware for its applicability in weather and climate modelling. We expand previous studies on inexact techniques, in particular probabilistic pruning, to floating point arithmetic units and derive several simulated set-ups of pruned hardware with reasonable levels of error for applications in atmospheric modelling. The set-up is tested on the Lorenz ‘96 model, a toy model for atmospheric dynamics, using software emulation for the proposed hardware. The results show that large parts of the computation tolerate the use of pruned hardware blocks without major changes in the quality of short- and long-time diagnostics, such as forecast errors and probability density functions. This could open the door to significant savings in computational cost and to higher resolution simulations with weather and climate modelsItem Realizing Ultra Energy-efficient Hardware Systems through Inexact Computing(2014-04-25) Lingamneni, Avinash; Palem, Krishna V.; Burrus, C. Sidney; Vardi, Moshe Y.; Enz, ChristianIn this dissertation, novel methodologies for designing energy-efficient hardware systems that deliver just "good-enough" results are proposed by leveraging the principles of inexact computing, wherein perceptually- or statistically-acceptable accuracy degradation is permitted in exchange for substantial hardware savings. These inexact computing systems are of particular relevance today owing to the widely acknowledged limit to the exponentially improving resource-savings sustained by Moore's law driven technology scaling as well as the emergence of a large classes of workloads (in particular, embedded, multimedia and Recognition, Mining and Synthesis (RMS) applications) that could still process information usefully with unreliable or error-prone elements. This thesis proposes several inexact design methodologies to efficiently realize energy-efficient hardware systems by intentionally rendering reliable components unreliable. These inexact systems are shown to produce ``good-enough" results, judged through domain-specific quality evaluation metrics, in a wide variety of error-resilient applications, while consuming significantly less hardware resources—quantified through energy consumed, critical path delay and/or area occupied. The proposed inexact design techniques span several layers of design abstraction: voltage overscaling (overclocking) and gate sizing at the physical layer; inexact logic minimization at the logic-layer; probabilistic pruning and compensation buddies at the architectural-layer and waveform shaping at the algorithm-layer. Furthermore, a cross-layer co-design framework is presented that creates a symbiotic interaction between the techniques from different layers of abstraction to maximize the resulting energy gains for a targeted accuracy loss while overcoming the drawbacks of individual techniques; this framework uses machine-learning approaches to further enhance the cost-accuracy tradeoff gains in DSP hardware systems. The effectiveness of the proposed techniques has been validated through extensive experimental simulations and backed up by two ASIC chip fabrications—64-bit inexact arithmetic adders in 180nm(LP) and 256-point quality-tunable Fast Fourier Transform (FFT) accelerators in 65nm process technology. The utility of the proposed techniques is also shown in applications from other domains including image/multimedia codecs as well as neural network accelerators—all of which can tolerate inaccuracies to varying extents and can synthesize sufficient information even from inaccurate computations.