Browsing by Author "Li, Dai"

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    Battery-less Transmitter and Frequency-Agile Receiver for IoT Applications
    (2018-04-19) Li, Dai; Babakhani, Aydin
    Recent increasing demands for IoT device, wearable device and biomedical implants have been calling for more low power, energy efficient and highly integrated devices from electronic industry. Implementing transmitter and energy-harvesting circuits on a same chip is a good way to provide battery-less systems for data transmission in wireless sensor networks. Prior wireless powered devices work used sub-gigahertz microwaves and require very large antenna for energy harvesting, which prevents their application in biomedical implants and single-chip integration. Our work on battery-less transmitter integrated on-chip antenna for 8 to 10 GHz wireless energy harvesting. This approach reduced antenna size and provided stable 10uW energy source for duty-cycled operating transmitter. The transmitter used On-Off Key (OOK) modulation. Oscillator, a class-E power amplifier and a dipole on-chip antenna are the main components of the transmitter. The transmitter operates at 1.46GHz and consumes 25mW power. The on-chip antenna is matched to the transmitter at 1.46GHz and could radiate up to -20dBm power into the air. By modulating from an external signal source, the data rate can be as high as 50M Bit/sec. The transmitter is able to harvest power from a radiating antenna 30cm away from the chip with a size of 7.4mm2 and transmit data back. Thus it is suitable for biomedical implant and wearable devices. On the other hand, our work introduced a frequency-agile receiver that detect and switch to the most power efficient channel quickly. The receiver consists of a band-switching low noise amplifier (LNA), an all-digital-phase-locked-loop (ADPLL), a power detector and a successive approximation analog to digital converter. The receiver worked at 4.3 to 5.7GHz and provide quick band-switching on the LNA and ADPLL. It provides quick and accurate channel selection in quickly changing environments.
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    Hardware Security Primitives for Resource-Constrained Devices
    (2021-08-13) Li, Dai; Yang, Kaiyuan
    With the number of IoT devices surpassed global population, the shortage of energy, area and security of IoT presents a challenge to its application in wider scenarios. The issues of cyber security, information and privacy have been critical to the involvement of edge devices to industry, finance and personal life. Modern edge devices experience various attacks from different dimensions. In the physical domain, reverse-engineering, micro-probing and optical-reading are some widely used techniques to hack IC structure and data information. Trojan injection, side-channel analysis, web attacks are some popular way to carry out non-invasive attack. For resource-constrained devices, these attacks are especially efficient. There are mature solutions such as trusted platform module (TPM) and trusted execution environment (TEE) deployed by Intel and ARM to protect devices from some attacks. They provide key generation and storage, cryptography algorithms and other functions to ensure the confidentiality and integrity of device. But they come with issues of high area and energy budget for resource-constrained devices. Some algorithms they use such as RSA can be cracked by quantum computer easily. To provide better security for edge devices with affordable cost and robustness against prevalent attacks and quantum computers, we designed memory-centric hardware to accelerate the root and chain of trust of miniaturized area and energy. Three major projects were implemented to realize this concept. First, a 562-feature-square physically unclonable function provided state-of-the-art energy and area for secure key generation. Second, an 8-T CAM based network intrusion detection system performed signature-based intrusion detection for distributed IoT devices with 1.54-fJ/Byte/Search efficiency. The automata engine with system-level and circuit-level co-design presented the first silicon solution for IoT hardware firewall. Third, a processing-in-memory accelerator (PQC) for post-quantum cryptography was implemented to provide compact and low-power engine for PQC computation. A range-matching CAM-based cumulative-distribution-table (CDT) sampler was implemented to achieve 8pJ/sample energy efficiency and 100M sample/s throughput. A 6-T SRAM-based near-memory accelerator for number theoretical transformation was implemented for ultra-compact single-bank NTT operation for Ring-LWE cryptography. The use of in- and near-memory computation in security achieved area and energy efficiency compatible with low-power IoT applications.