Browsing by Author "Kota, Kishore"
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Item Architectural, Numerical and Implementation Issues in the VLSI Design of an Integrated CORDIC-SVD Processor(1991-05-20) Kota, Kishore; Center for Multimedia Communications (http://cmc.rice.edu/)The Singular Value Decomposition (SVD) is an important matrix factorization with applications in signal processing, image processing and robotics. This thesis presents some of the issues involved in the design of an array of special-purpose processors connected in a mesh, for fast real time computation of the SVD. The systolic array implements the Jacobi method for the SVD. This involves plane rotations and inverse tangent calculations and is implemented efficiently in hardware using the Coordinate Rotation Digital Computer (CORDIC) technique. A six chip custom VLSI chip set for the processor was initially developed and tested. This helped identify several bottlenecks and led to an improved design of the single chip version. The single chip implementation incorporates several enhancements that provide greater numerical accuracy. An enhanced architecture which reduces communication was developed within the constraints imposed by VLSI. The chips were fabricated in a 2.0 micron CMOS n-well process using a semicustom design style. The design cycle for future chips can be considerably reduced by adopting a symbolic layout style using high-level VLSI tools such as Octtools from the University of California, Berkeley. Previous architectures for CORDIC processors provided log n bits to guard n bits from truncation errors. A detailed error analysis of the CORDIC iterations indicates that extra guard bits are required to guarantee n bits of precision. In addition, normalization of the input values ensures greater accuracy in the calculations using CORDIC. Anovel normalization scheme for CORDIC which has O(n1.5) area complexity as opposed to O(n²) area it would take if this were implemented using conventional hardware, is described. Data dependencies in the array allow only a third of the processors to be active at any time. Several timing schemes which improve the utilization by overlapping communication and computation are developed and evaluated. It is shown that it is possible to effectively utilize all the idle time in the array by concurrently computing the left and right singular vectors along with the singular values. Future versions of the processor can implement these schemes.Item Architectural, numerical and implementation issues in the VLSI design of an integrated CORDIC-SVD processor(1991) Kota, Kishore; Cavallaro, Joseph R.This thesis describes the design of a systolic array for computing the Singular Value Decomposition (SVD) based on the Brent, Luk, Van Loan array. The use of COordinate Rotation DIgital Computer (CORDIC) arithmetic results in an efficient VLSI implementation of the processor that forms the basic unit of the array. A six-chip custom VLSI chip set for the processor was initially designed, fabricated in a 2.0$\mu$ CMOS n-well process, and tested. The CORDIC Array Process Element (CAPE), a single chip implementation, incorporates several enhancements based on a detailed error analysis of fixed-point CORDIC. The analysis indicates a need to normalize input values for inverse tangent computations. This scheme was implemented using a novel method that has $O(n\sp{1.5})$ hardware complexity. Use of previous techniques to implement such a normalization would require $O(n\sp2)$ hardware. Enhanced architectures, which reduce idle time in the array either through pipelining or by improving on a broadcast technique, are also presented.Item CAPE - VLSI Implementation of a Systolic Processor Array: Architecture, Design and Testing(1991-06-20) Hemkumar, Nariankadu D.; Kota, Kishore; Cavallaro, Joseph R.; Center for Multimedia Communications (http://cmc.rice.edu/)The SVD is an important matrix decomposition in many real-time signal processing, image processing and robotics applications. Special-purpose processor arrays can achieve significant speed-up over conventioinal architectures through the use of efficient parallel algorithms. The Cordic Array Processor Element (CAPE) is a single chip VLSI implementation of a processor element for the Brent-Luk-VanLoan systolic array which computes the SVD of a real matrix. The array utilizes CORDIC (Co-ordinate Rotation Digital Computer) arithmetic to perform the vector rotations and inverse tangent calculations in hardware. A six-chip prototype of the processor has been implemented as TinyChips using the MOSIS fabricatioin service. Experience gained from designing the prototype helped in the design of integrated single chip version. The chip has been implemented on a 5600 x 6900ì die in a 2ì n-well scalable CMOS process.Item CMOS Processor Element For A Fault-Tolerant SVD Array(1993-07-20) Kota, Kishore; Cavallaro, Joseph R.; Center for Multimedia Communications (http://cmc.rice.edu/)This paper describes the VLSI implementation of a CORDIC based processor element for use in a fault-reconfigurable systolic array to compute the Singular Value Decomposition (SVD) of a matrix. The chip implements a time redundant fault tolerance scheme, which allows processors adjacent to a faulty processor to act as computation backup during the systolic idle time. Also, processors around a fault collaborate to reroute data around the faulty processor. This form of time redundancy is attractive when tolerance to a few faults needs to be achieved with little hardware overhead. Many of the proposed systolic array architectures for SVD are made of slightly dissimilar processors. We show that a physically uniform stucture of the array simplifies the design, especially for fault-reconfigurable processor arrays. Our implementation required the addition of a number of architectural features to ease custom VLSI design. We eliminated the special pyhysical edge connections proposed by earlier mesh architectures by adding extra programmablility to the chip and embedding the original array in a regular toroidal structure. This allows undersized problems to be mapped onto the same physical array without padding the matrix with rows or colums of zeros. In addition, an entire row or column may be bypassed without the need for external switches, thus providing an extra degree of fault tolerance. The chip was designed in a CMOS double-metal 2ì process and is 8954u x 7840ì. The overheads incurred in adding the time redundancy were an increase of about 40% in the number of controller states and a backup set of register to store the faulty neighbor's data. The array was initially simulated at t highter level using VHDL descriptions and schematic capture software. This was then mapped to a custon chip using rapid-prototyping techniques.Item A Normalization Scheme to Reduce Numerical Errors in Inverse Tangent comptations on a Fixed-point CORDIC Processor(1992-05-20) Kota, Kishore; Cavallaro, Joseph R.; Center for Multimedia Communications (http://cmc.rice.edu/)Coordinate Rotation Digital Computer (CORDIC) is a unified arithmetic algorithm that allows efficient VLSI implementation of several elementary functions. Many special-purpose systems for real-time signal processing application use a fixed-point representation of numbers due to the ease of implementation. An analysis of fixed-point CORDIC in the Y-reduction mode, which allows computation of the inverse tangent function, shows that unnormalized input values can result in large numerical errors. This paper presents a method to integrate the normalization operatioin with CORDIC iterations for efficient implementation in 0(n1.5) hardware.Item Numerical Accuracy and Hardware Tradeoffs for CORDIC Arithmetic for Special-Purpose Processors(1993-07-20) Kota, Kishore; Cavallaro, Joseph R.; Center for Multimedia Communications (http://cmc.rice.edu/)The coordinate rotation digital computer (CORDIC) algorithm is used in numerous special-purpose systems for real-time signal processing applications. It is desirable to use fixed-point CORDIC units in such systems, since the low complexity, compared to floating-point, allows multiple CORDIC units and additional hardware to be integrated on the same chip. However, an analysis of fixed-point CORDIC in the Y-reduction mode, which allows computation of the inverse tangent function, shows that unnormalized input values can result in large numerical errors. This paper describes two approaches to tackle the numerical accuracy problem. The first approach builds on a fixed-point CORDIC unit and eliminates the problem by including additional hardware for normalization. This paper presents a method to integrate the normalization operation with the CORDIC iterations for efficient implementation in "0(n1.5)" hardware. The second solution to the accuracy problem is to use a floating-point CORDIC unit but reduce the implementation complexity by using a hybrid architecture. We present arguments to support the use of such an architecture in certain special purpose arrays.Item Parallel Algorithms and Architectures for near-far resistant CDMA acquisition(1996-05-20) Kota, Kishore; Center for Multimedia Communications (http://cmc.rice.edu/)Subspace-based algorithms are a class of algorithms for estimation problems in array signal processing and more recently near-far resistant Code Division Multiple Access (CDMA) acquisition problems. Subspace-based algorithms are based on estimating signal or noise subspaces from the received data vectors and then performing some form of optimization to estimate the desired parameters. This thesis presents two new parallel algorithms applicable in the estimation of signal or noise subspaces from the received data vectors. The first algorithm is a pipelined SVD algorithm which allows pipelining of multiple independent singular value decomposition (SVD) problems on a single processor array. The resultant algorithm uses the exibility provided by the Jacobi algorithm by defining a new parallel ordering to result in a simple uniform array in which all communication including the initial load and the final unload operations are pipelined. The second algorithm described in this thesis is a sliding window SVD updating algorithm where the signal or noise subspace is updated whenever a new observation vector is received by applying a fixed-length window over the data. An important result shown in this thesis is that an important property ofdowndating problems, known as relational stability, extends to a hybrid fixed-point and oating-point algorithm. By performing most of the computation in fixed-point, significant gains in implementation complexity may be realized. This thesis also extends an SVD algorithm originally developed for an exponential window to the sliding window problem through the use of carefully implemented hyperbolic rotations. A second major topic of this thesis is demonstrating the applicability of a number of algorithms and architectures developed in the array signal processing area to the near-far resistant acquisition problem in CDMA communication systems. This thesis classiffies the available literature in this area and performs a qualitative analysis of the different algorithms from the view of applicability towards the CDMA problem. The third contribution of this thesis is a unified parallel architecture to implement the backend portions of the CDMA problem. Through the combination of a matrix vector multiplication array, an inner product computation array and an array of processors to perform second-order or third-order polynomial optimization a parallel architecture to implement the backend processing in the CDMA problem is realized.Item Parallel algorithms and architectures for near-far resistant CDMA acquisition(1996) Kota, Kishore; Cavallaro, Joseph R.Subspace-based algorithms are a class of algorithms for estimation problems in array signal processing and more recently near-far resistant Code Division Multiple Access (CDMA) acquisition problems. Subspace-based algorithms are based on estimating signal or noise subspaces from the received data vectors and then performing some form of optimization to estimate the desired parameters. This thesis presents two new parallel algorithms applicable in the estimation of signal or noise subspaces from the received data vectors. The first algorithm is a pipelined SVD algorithm which allows pipelining of multiple independent singular value decomposition (SVD) problems on a single processor array. The resultant algorithm uses the flexibility provided by the Jacobi algorithm by defining a new parallel ordering to result in a simple uniform array in which all communication including the initial load and the final unload operations are pipelined. The second algorithm described in this thesis is a sliding window SVD updating algorithm where the signal or noise subspace is updated whenever a new observation vector is received by applying a fixed-length window over the data. An important result shown in this thesis is that an important property of downdating problems, known as relational stability, extends to a hybrid fixed-point and floating-point algorithm. By performing most of the computation in fixed-point, significant gains in implementation complexity may be realized. This thesis also extends an SVD algorithm originally developed for an exponential window to the sliding window problem through the use of carefully implemented hyperbolic rotations. A second major topic of this thesis is demonstrating the applicability of a number of algorithms and architectures developed in the array signal processing area to the near-far resistant acquisition problem in CDMA communication systems. This thesis classifies the available literature in this area and performs a qualitative analysis of the different algorithms from the view of applicability towards the CDMA problem. The third contribution of this thesis is a unified parallel architecture to implement the backend portions of the CDMA problem. Through the combination of a matrix vector multiplication array, an inner product computation array and an array of processors to perform second-order or third-order polynomial optimization a parallel architecture to implement the backend processing in the CDMA problem is realized.Item Parallel algorithms and architectures for subspace based channel estimation for CDMA communication systems(1996-08-20) Sengupta, Chaitali; Kota, Kishore; Cavallaro, Joseph R.; Center for Multimedia Communications (http://cmc.rice.edu/)This paper presents an overview and results from an ongoing research project to study parallel algorithms for the acquisition of Code Division Multiple Access (CDMA) communication signals. The goal of this research isto evaluate a class of related algorithms and architectures for the acquisition problem and map them onto parallel architectures containing DSPs. The algorithms used are generally termed subspace-based algorithms, since they involve computation of subspaces of the vector space spanned by certain observation vectors. This paper presents results from some preliminary implementations of such a subspace-based algorithm on the Texas Instruments TMS320C40 Parallel Processing Development System.Item Pipelining Multiple SVDs On A Single Processor Array(1994-07-20) Kota, Kishore; Cavallaro, Joseph R.; Center for Multimedia Communications (http://cmc.rice.edu/)We present a new family of architectures for processor arrays to implement Jacobi SVD which allow systolic loading and unloading of input and result matrices. Unlike most of the previous SVD arrays in the literature, our architectures do not require special handling of external I/O and hence are closer to the traditional concept of systolic architectures. The boundary processors communicate with the host the same way any of the interior processors communicate with their neighbors. The arrays are surprisingly uniform and simple. The various architectures in the family represent different throughput-hardware tradeoffs corresponding to the degree to which the multiple seeeps have been unrolled and determine the number of independent SVDs which may be pipelined on the array. We achieve systolic loading by using the flexibility provided by the cyclic Jocobi method on the order in which pivot pairs may be chosen. The array operates on the matrix data even as it is being loaded. Once the pipeline is full, the ordering is very similar to odd-even ordering. Our ordering is equivalent to cyclic-by-rows ordering and hence the algorithm is guaranteed to converge. Our systolic loading scheme is very important in an I/O limited system, since it allows more communication to occur in paralled, where the communication includes the loading and unloading operations. The array with the highest throughput in our family of architectures, which implement one-sided Jacobi (either Hestenes' method or Eberlein and Park's method), is a linear array of processors with unidirectional links between neighbors. The architectures with lower throughput require fewer processors connected in a ring, allowing data to recirculate among the processors. The input matrix is loaded one column at a time from the left and the results stream out one colum at a time from the right.