Browsing by Author "He, Yan"

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    Low-Cost Circuit Primitives for Physically Securing IoT Devices
    (2024-04-17) He, Yan; Yang, Kaiyuan
    With the rapid advancement of Internet of Things (IoT) technology, securing edge devices has become critically important. This need stems from the increasing interaction of users with a wide range of mobile and embedded devices. While the expansion of IoT has simplified access, it has also heightened the vulnerability of these devices to physical security threats. Malicious actors are now adept at bypassing traditional software security measures to exploit physical vulnerabilities and access sensitive data. Consequently, bolstering the physical security of IoT hardware, particularly at the edge, is essential. Existing ASIC solutions for mitigating these physical threats, while effective, often come with high costs, either in terms of power consumption, performance trade-offs, silicon area overhead, or design complexity. These factors contribute to substantial implementation costs, rendering such measures impractical for many edge applications, especially considering the narrow profit margins typical of IoT devices. In my Ph.D. research, I have focused on creating a suite of low-cost, hardware-enabled security solutions for IoT applications. This endeavor involved completing four key projects, each targeting a critical area of vulnerability in this rapidly expanding field: the generation of both static and dynamic keys, and countermeasures against Side-Channel Attacks (SCAs) and Fault Injection Attacks (FIAs). To reduce the necessity for extensive testing and post-processing of the existing static key generation schemes, I designed a highly stable and efficient Physically Unclonable Function (PUF). Furthering the dynamic key generation, I designed a high-speed, fully synthesizable True Random Number Generator (TRNG), showcasing robust performance under various environmental conditions. To enhance the resistance against SCAs, I designed a Digital Low Dropout Regulator (DLDO) that provides strong SCA resistance while maintaining high regulation performance, which is an innovative approach that utilizes existing power management structures to enhance resistance against SCAs. Lastly, I designed a Fully Synthesizable Design-Agnostic Fault Injection Monitor, which stands out in defending against FIAs due to its comprehensive attack coverage, improved power efficiency, area, and design simplicity. These advancements represent a step forward in improving IoT device security while reducing the cost of said security. By making sophisticated security measures more accessible, my research addresses a critical need in the IoT field, where budget limitations often hinder the implementation of strong security protocols. The affordability of these security enhancements allows for their integration even in IoT devices with lower profit margins. As a result, this contributes to a more secure and safer IoT environment, benefiting manufacturers and consumers alike.
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    Phsyically Secure Cryptographic Hardware
    (2022-01-27) He, Yan; Yang, Kaiyuan
    With the recent booming of Internet of Things (IoT) technology, people now have physical access to various mobile and embedded devices. A malicious party can bypass software security and gain valuable information through physical attacks. Therefore, the physical security of IoT hardware is becoming increasingly important. Side-channel attack (SCA) is one of the major security concerns. Attackers can gain information inside the chip through physical side channels, like power consumption, electro-magnetic (EM) radiation, timing, etc. Existing protections induce large performance and energy overhead, and usually require design-specific modifications. We propose and demonstrate prototype chips for a SCA-resistant, design agnostic, high-performance digital low drop-out regulator (DLDO). We show that the proposed design can not only achieve state-of-the-art regulation performance, it also improves >20000x Power-SCA resistance (MTD) of an AES engine with little design overheads. Secure key storage is another important issue. Traditionally, a permanent key is externally written in non-volatile memory (NVM). This approach is dubious both in its vulnerability to hostile attackers and its area and power utilization. Physically Unclonable Function (PUF), on the other hand, generates a unique key for each device, has a small area and power consumption, and is secure against various tampering methods. Previous PUFs have stability issues that require large design or testing costs to overcome. We propose Automatic and Self-Checking and Healing (ASCH) PUF with dual modes of operation that aims to achieve a fully stabilized PUF with reduced cost. Silicon prototype shows ASCH-PUF has a small design overhead, achieves 0% instability (BER) with no testing cost, and has >2x reduced masking ratio compared with previous approaches.