Browsing by Author "Covington, Richard Glenn"
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Item CSIM: an efficient implementation of a discrete-event simulator(1985) Covington, Richard Glenn; Jump, J. Robert; Sinclair, James B.; Briggs, Faye A.We discuss the design and efficient implementation of the Rice C Simulation Package (CSIM), a software tool, written in C, and designed to work compatibly with the standard C compiler. The tool provides support for discrete-event or process-interaction simulation, especially for digital logic and queuing theoretic models. We first discuss the existing modeling formalism necessary to abstract a discrete-event model from a real system. We then introduce a set of primitives which are sufficient for preparing an algorithmic specification of the abstract model. Finally, we report on the successful realization of the primitives, discussing or clarifying existing modeling methodology and establishing new methodology when necessary. We also describe the implementation of a recently proposed efficient event list algorithm (the TL algorithm), and present a study of its complexity.Item Validation of Rice Parallel Processing Testbed applications(1989) Covington, Richard Glenn; Jump, J. RobertThe Rice Parallel Processing Testbed (RPPT) is a collection of software tools for simulating the interaction of parallel programs and parallel architectures. The testbed uses a novel technique called execution-driven simulation, whereby the pseudo-concurrent execution of a parallel algorithm, augmented by profiling code, is used to drive the discrete-event simulation of a parallel architecture. This technique is intermediate between the high accuracy and low computational efficiency of instruction-level simulations and the less accurate but high efficiency statistical distribution-driven simulations, effectively combining attractive features of both of these techniques. The technique provides estimates of overall execution time, as well as more detailed performance indices such as communication vs. computation time, message passing traffic, and processor utilization. The methodology and implementation of the testbed are discussed at length and are compared with recently published related projects. The implementation has been a collective effort involving several people, and the author's contribution to the effort is outlined. Testbed predictions are given for a set of parallel numerical algorithms--LU decomposition, eigenvalue-eigenvector determination, FFT--simulated for a hypercube, and the predictions are validated against measurement of actual program execution on an Intel iPSC 16-node hypercube.