Browsing by Author "Chandrasekhar, Vikram"
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Item Enabling a “Use-or-Share” Framework for PAL–GAA Sharing in CBRS Networks via Reinforcement Learning(IEEE, 2019) Tarver, Chance; Tonnemacher, Matthew; Chandrasekhar, Vikram; Chen, Hao; Ng, Boon Loong; Zhang, Jianzhong; Cavallaro, Joseph R.; Camp, JosephBy implementing reinforcement learning-aided listen-before-talk (LBT) schemes over a citizens broadband radio service (CBRS) network, we increase the spatial reuse at secondary nodes while minimizing the interference footprint on higher-tier nodes. The federal communications commission encourages “use-or-share” policies in the CBRS band across the priority access license (PAL)-general authorized access (GAA) priority tiers by opportunistically allowing the lower-priority GAA nodes to access unused higher-priority PAL spectrum. However, there is currently no mechanism to enable this cross-tier spectrum sharing. In this paper, we propose and evaluate LBT schemes that allow opportunistic access to PAL spectrum. We find that by allowing LBT in a two carrier, two eNB scenario, we see upward of 50% user perceived throughput (UPT) gains for both eNBs. Furthermore, we examine the use of ${Q}$ -learning to adapt the energy-detection threshold (EDT), combating problematic topologies, such as hidden and exposed nodes. With merely a 4% reduction in primary node UPT, we see up to 350% gains in average secondary node UPT when adapting the EDT of opportunistically transmitting nodes.Item Handset Detector Architectures for DS-CDMA Wireless Systems(2002-05-20) Livingston, Frank; Chandrasekhar, Vikram; Vaya, Mani; Cavallaro, Joseph R.; Center for Multimedia Communications (http://cmc.rice.edu/)This paper investigates detector architectures for wireless handsets employing DS-CDMA. The code-matched filter (MF) and minimum output energy (MOE) detectors are analyzed with respect to fixed-point arithmetic behavior. Architectures employing fixed-point arithmetic are then proposed for these detectors. The maximum throughput of these architectures and the associated costs in terms of area usage and power consumption are evaluated. Results of the fixed-point analysis indicate that the MOE detector is more susceptible to quantization than the MF detector. Results of implementation indicate that the superior performance of the MOE detector is achieved at a considerably higher cost in terms of area usage and power consumption. Finally, comparison of hardware implementation with software-based DSP implementation indicates that software approaches result in considerably lower throughputs.Item Reducing Dynamic Power Consumption in Next Generation DS-CDMA Mobile Communication Receivers(2003-06-20) Chandrasekhar, Vikram; Livingston, Frank; Cavallaro, Joseph R.; Center for Multimedia Communications (http://cmc.rice.edu/)Reduction of the power consumption in portable wireless receivers is an important consideration for next-generation cellular systems specified by standards such as the UMTS, IMT2000. This paper explores the architectural design-space and methodologies for reducing the dynamic power dissipation in the Direct Sequence Code Division Multiple Access (DS-CDMA) downlink RAKE receiver. Starting with a reference implementation of the DS-CDMA RAKE receiver, we demonstrate design methodologies for achieving significant power reduction, while highlighting the corresponding performance trade-offs. At the algorithm level, we investigate the tradeoffs of reduced precision and arithmetic complexity on the receiver performance. We then present two architectures for implementing the reference and reduced complexity receivers, and analyze these architectures with respect to their dynamic power dissipation. Our findings report that reduction in precision from a 16 bit to a 10 bit data-path is found to yield significant power savings of 25.6% in the reference RAKE receiver architecture, with a performance loss of less than 1 dB. Further, a power reduction of upto 24.65% is achieved in a 16 bit data-path for the reduced complexity RAKE receiver compared to the reference architecture, with a performance loss of less than 2 dB. Although there is a tradeoff in performance, adaptive power saving is very important for mobile wireless terminals. The combined effect of reduced precision and complexity reduction leads to a 37.44% savings in baseband processing power.Item Reducing dynamic power consumption in next generation DS-CDMA mobile communication receivers(Inderscience Enterprises Ltd., 2008-09-01) Chandrasekhar, Vikram; Livingston, Frank; Cavallaro, Joseph R.; Center for Multimedia CommunicationReduction of the power consumption in portable wireless receivers is important for cellular systems, including UMTS and IMT2000. This paper explores the architectural design-space and methodologies for reducing the dynamic power dissipation in the Direct Sequence Code Division Multiple Access (DS-CDMA) downlink RAKE receiver. At the algorithm level, we investigate the tradeoffs of reduced precision and arithmetic complexity on the receiver performance. We then present and analyse two architectures for implementing the reference and reduced complexity receivers, with respect to dynamic power dissipation. The combined effect of reduced precision and complexity reduction leads to a 37.44% power savings.Item Reducing dynamic power consumption in next generation DS-CDMA mobile communication receivers(2003) Chandrasekhar, Vikram; Cavallaro, Joseph R.Reduction of the power consumption in portable wireless receivers is an important consideration for next-generation cellular systems specified by standards such as the UMTS, IMT2000. This thesis explores the design-space for reducing the dynamic power dissipation in a RAKE receiver for the Direct Sequence Code Division Multiple Access (DS-CDMA) downlink. Starting with a reference implementation of the DS-CDMA RAKE receiver, we demonstrate design methodologies for achieving significant power reduction, while high-lighting the corresponding performance trade-offs. At the algorithm level, we investigate the impact of reduced precision and arithmetic complexity on the performance of the DS-CDMA RAKE receiver. We then present architectures for implementing the reference and reduced complexity DS-CDMA RAKE receivers, and analyze these architectures with respect to their dynamic power dissipation. Finally, we analyze clock-gating techniques for reducing the activity rate in both the architectures to achieve further power reduction.Item Reducing Dynamic Power Consumption in Next Generation DS-CDMA Mobile Communication Receivers(2002-08-01) Chandrasekhar, Vikram; Center for Multimedia Communications (http://cmc.rice.edu/)Reduction of the power consumption in portable wireless receivers is an important consideration for next-generation cellular systems specified by standards such as the UMTS, IMT2000. This thesis explores the design-space for reducing the dynamic power dissipation in a RAKE receiver for the Direct Sequence Code Division Multiple Access (DS-CDMA) downlink. Starting with a reference implementation of the DS-CDMA RAKE receiver, we demonstrate design methodologies for achieving significant power reduction, while highlighting the corresponding performance trade-offs. At the algorithm level, we investigate the impact of reduced precision and arithmetic complexity on the performance of the DS-CDMA RAKE receiver. We then present architectures for implementing the reference and reduced complexity DS-CDMA RAKE receivers, and analyze these architectures with respect to their dynamic power dissipation. Finally, we analyze clock-gating techniques for reducing the activity rate in both the architectures to achieve further power reduction.