Browsing by Author "Bhattacharyya, Shuvra S."

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    Dataflow Modeling and Design for Cognitive Radio Networks
    (8th International Conference on Cognitive Radio Oriented Wireless Networks, 2013-10-01) Wang, Lai-Huei; Bhattacharyya, Shuvra S.; Vosoughi, Aida; Cavallaro, Joseph R.; Juntti, Markku; Boutellier, Jani; Silven, Olli; Valkama, Mikko; CMC
    Cognitive radio networks present challenges at many levels of design including configuration, control, and crosslayer optimization. In this paper, we focus primarily on dataflow representations to enable flexibility and reconfigurability in many of the baseband algorithms. Dataflow modeling will be important to provide a layer of abstraction and will be applied to generate flexible baseband representations for cognitive radio testbeds, including the Rice WARP platform. As RF frequency agility and reconfiguration for carrier aggregation are important goals for 4G LTE Advanced systems, we also focus on dataflow analysis for digital pre-distortion algorithms. A new design method called parameterized multidimensional design hierarchy mapping(PMDHM) is presented, along with initial speedup results from applying PMDHM in the mapping of channel estimation onto a GPU architecture.
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    GPU-based Acceleration of Symbol Timng Recovery
    (IEEE, 2012-12-20) Kim, Scott C.; Plishker, William L.; Bhattacharyya, Shuvra S.; Cavallaro, Joseph R.; CMC
    This paper presents a novel implementation of graphics processing unit (GPU) based symbol timing recovery using polyphase interpolators to detect symbol timing error. Symbol timing recovery is a compute intensive procedure that detects and corrects the timing error in a coherent receiver. We provide optimal sample-time timing recovery using a maximum likelihood (ML) estimator to minimize the timing error. This is an iterative and adaptive system that relies on feedback, therefore, we present an accelerated implementation design by using a GPU for timing error detection (TED), enabling fast error detection by exploiting the 2D filter structure found in the polyphase interpolator. We present this hybrid/ heterogeneous CPU and GPU architecture by computing a low complexity and low noise matched filter (MF) while simultaneously performing TED. We then compare the performance of the CPU vs. GPU based timing recovery for different interpolation rates to minimize the error and improve the detection by up to a factor of 35. We further improve the process by utilizing GPU optimization and performing block processing to improve the throughput even more, all while maintaining the lowest possible sampling rate.