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Browsing ECE Publications by Author "Adve, Sarita V."
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Item Analytic Evaluation of Shared-Memory Systems with ILP Processors(1998-06-20) Sorin, Daniel J.; Pai, Vijay S.; Adve, Sarita V.; Vernon, Mary K.; Wood, David A.; CITI (http://citi.rice.edu/)NoneItem Code Transformations to Improve Memory Parallelism(2000-05-20) Pai, Vijay S.; Adve, Sarita V.; CITI (http://citi.rice.edu/)Current microprocessors incorporate techniques to exploit instruction-level parallelism (ILP). However, previous work has shown that these ILP techniques are less effective in removing memory stall time than CPU time, making the memory system a greater bottleneck in ILP-based systems than in previous-generation systems. These deficiencies arise largely because applications present limited opportunities for an out-of-order issue processor to overlap multiple read misses, the dominant source of memory stalls. This work proposes code transformations to increase parallelism in the memory system by overlapping multiple read misses within the same instruction window, while preserving cache locality. We present an analysis and transformation framework suitable for compiler implementation. Our simulation experiments show execution time reductions averaging 20% in a multiprocessor and 30% in a uniprocessor. A substantial part of these reductions comes from increases in memory parallelism. We see similar benefits on a Convex Exemplar.Item Code Transformations to Improve Memory Parallelism(1999-11-20) Pai, Vijay S.; Adve, Sarita V.; CITI (http://citi.rice.edu/)NoneItem Comparing and Combining Read Miss Clustering and Software Prefetching(2001-09-20) Pai, Vijay S.; Adve, Sarita V.; CITI (http://citi.rice.edu/)NoneItem A Customized MVA Model for ILP Multiprocessors(1998-04-20) Sorin, Daniel J.; Vernon, Mary K.; Pai, Vijay S.; Adve, Sarita V.; Wood, David A.; CITI (http://citi.rice.edu/)This paper provides the customized MVA equations for an analytical model for evaluating architectural alternatives for shared-memory multiprocessors with processors that aggressively exploit instruction-level parallelism (ILP). Compared to simulation, the analytical model is many orders of magnitude faster to solve, yielding highly accurate system performance estimates in seconds.Item An Evaluation of Memory Consistency Models for Shared-Memory Systems with ILP Processors(1996-10-20) Pai, Vijay S.; Ranganathan, Parthasarathy; Adve, Sarita V.; Harton, Tracy; CITI (http://citi.rice.edu/)NoneItem The Impact of Exploiting Instruction-Level Parallelism on Shared-Memory Multiprocessors(1999-02-20) Pai, Vijay S.; Ranganathan, Parthasarathy; Abdel-Shafi, Hazim; Adve, Sarita V.; CITI (http://citi.rice.edu/)Current microprocessors incorporate techniques to aggressively exploit instruction-level parallelism (ILP). This paper evaluates the impact of such processors on the performance of shared-memory multiprocessors, both without and with the latency-hiding optimization of software prefetching. Our results show that, while ILP techniques substantially reduce CPU time in multiprocessors, they are less effective in removing memory stall time. Consequently, despite the inherent latency tolerance features of ILP processors, we find memory system performance to be a larger bottleneck and parallel efficiencies to be generally poorer in ILP- based multiprocessors than in previous generation multiprocessors. The main reasons for these deficiencies are insufficient opportunities in the applications to overlap multiple load misses and increased contention for resources in the system. We also find that software prefetching does not change the memory bound nature of most of our applications on our ILP multiprocessor, mainly due to a large number of late prefetches and resource contention. Our results suggest the need for additional latency hiding or reducing techniques for ILP systems, such as software clustering of load misses and producer-initiated communication.Item The Impact of Instruction-Level Parallelism on Multiprocessor Performance and Simulation Methodology(1997-02-20) Pai, Vijay S.; Ranganathan, Parthasarathy; Adve, Sarita V.; CITI (http://citi.rice.edu/)NoneItem Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors(1999-01-20) Durbhakula, Murthy; Pai, Vijay S.; Adve, Sarita V.; CITI (http://citi.rice.edu/)NoneItem The Interaction of Software Prefetching with ILP Processors in Shared-Memory Systems(1997-06-20) Ranganathan, Parthasarathy; Pai, Vijay S.; Abdel-Shafi, Hazim; Adve, Sarita V.; CITI (http://citi.rice.edu/)NoneItem Recent Advances in Memory Consistency Models for Hardware Shared Memory Systems(1999-03-20) Adve, Sarita V.; Pai, Vijay S.; Ranganathan, Parthasarathy; CITI (http://citi.rice.edu/)NoneItem RSIM Reference Manual: Version 1.0(1997-08-20) Pai, Vijay S.; Ranganathan, Parthasarathy; Adve, Sarita V.; CITI (http://citi.rice.edu/)Simulation has emerged as an important method for evaluating new ideas in both uniprocessor and multiprocessor architecture. Compared to building real hardware, simulation provides at least two advantages. First it provides the flexibility to modify various architectural parameters and components and to analyze the benefits of such modification. Second, simulation allows for detailed statistics collection, providing a better understanding of the tradeoffs involved and facilitating further performance tuning. This document describes RSIM - the Rice Simulator for ILP Multiprocessors (Version 1.0). RSIM is an execution-driven simulator primarily designed to study shared-memory multiprocessor architectures built from state-of-the-art processors. Compared to other current publicly available shared-memory simulators, the key advantage of RSIM is that it supports a processor model that aggressively exploits instruction-level parallelism (ILP) and is more representative of current and near-future processors. Currently available shared-memory simulators assume a much simpler processor model, and can exhibit significant inaccuracies when used to study the behavior of shared-memory multiprocessors built from state-of-the-art ILP processors. A cost of the increased accuracy and detail of RSIM is that it is slower than simulators that do not model the processor. We have used RSIM at Rice for our research in computer architecture, as well as for undegraduate and graduate architecture courses covering both uniprocessor and multiprocessor architectures.Item RSIM: An Execution-Driven Simulator for ILP-Based Shared-Memory Multiprocessors and Uniprocessors(1997-10-20) Pai, Vijay S.; Ranganathan, Parthasarathy; Adve, Sarita V.; CITI (http://citi.rice.edu/)NoneItem Rsim: Simulating Shared-Memory Multiprocessors with ILP Processors(2002-02-20) Hughes, Christopher J.; Pai, Vijay S.; Ranganathan, Parthasarathy; Adve, Sarita V.; CITI (http://citi.rice.edu/)Rsim is a publicly available architecture simulator for shared-memory systems built from processors that aggressively exploit instruction-level parallelism. Modeling ILP features in a multiprocessor is particularly important for applications that exhibit parallelism among read misses.Item Using Speculative Retirement and Larger Instruction Windows to Narrow the Performance Gap between Memory Consistency Models(1997-06-20) Ranganathan, Parthasarathy; Pai, Vijay S.; Adve, Sarita V.; CITI (http://citi.rice.edu/)None