Sun, YangCavallaro, Joseph R.Zhu, YumingManish, Goel2012-06-062012-06-062010-01-01Y. Sun, J. R. Cavallaro, Y. Zhu and G. Manish, "Configurable and Scalable Turbo Decoder for 4G Wireless Receivers," vol. 2010, 2010.10.4018/978-1-61520-674-2http://scholar.google.com/scholar?cluster=3278205556887870384&hl=en&as_sdt=0,44https://hdl.handle.net/1911/64223The increasing requirements of high data rates and quality of service (QoS) in fourth-generation (4G) wireless communication require the implementation of practical capacity approaching codes. In this chapter, the application of Turbo coding schemes that have recently been adopted in the IEEE 802.16e WiMax standard and 3GPP Long Term Evolution (LTE) standard are reviewed. In order to process several 4G wireless standards with a common hardware module, a reconfigurable and scalable Turbo decoder architecture is presented. A parallel Turbo decoding scheme with scalable parallelism tailored to the target throughput is applied to support high data rates in 4G applications. High-level decoding parallelism is achieved by employing contention-free interleavers. A multi-banked memory structure and routing network among memories and MAP decoders are designed to operate at full speed with parallel interleavers. A new on-line address generation technique is introduced to support multiple Turbo interleaving patterns, which avoids the interleaver address memory that is typically necessary in the traditional designs. Design trade-offs in terms of area and power efficiency are analyzed for different parallelism and clock frequency goals.engError correction codesTurbo codesMAP algorithmBCJR algorithmTurbo decoderInterleaverWireless PHY4G receiverVLSI architectureBook chapter