Rajagopal, SridharBhashyam, SrikrishnaCavallaro, Joseph R.Aazhang, Behnaam2007-10-312007-10-312002-06-202001-09-18S. Rajagopal, S. Bhashyam, J. R. Cavallaro and B. Aazhang, "Efficient VLSI architectures for multiuser channel estimation in wireless base-station receivers," <i>Journal of VLSI Signal Processing,</i> vol. 31, no. 2, 2002.https://hdl.handle.net/1911/20224Journal PaperThis paper presents a reduced-complexity, fixed-point algorithm and efficient real-time VLSI architectures for multiuser channel estimation, one of the core baseband processing operations in wireless base-station receivers for CDMA. Future wireless base-station receivers will need to use sophisticated algorithms to support extremely high data rates and multimedia. Current DSP implementations of these algorithms are unable to meet real-time requirements. However, there exists massive parallelism and bit level arithmetic present in these algorithms than can be revealed and efficiently implemented in a VLSI architecture. We <i>it re-design</i> an existing channel estimation algorithm from an implementation perspective for a reduced complexity, fixed-point hardware implementation. Fixed point simulations are presented to evaluate the precision requirements of the algorithm. A dependence graph of the algorithm is presented and area-time trade-offs are developed. An area-constrained architecture achieves low data rates with minimum hardware, which may be used in pico-cell base-stations. A time-constrained solution exploits the entire available parallelism and determines the maximum theoretical data processing rates. An area-time efficient architecture meets real-time requirements with minimum area overhead.engreal-time implementationmultiuser channel estimationVLSIdependence graphsDSPW-CDMAfixed-pointJournal articlereal-time implementationmultiuser channel estimationVLSIdependence graphsDSPW-CDMAfixed-pointhttp://dx.doi.org/10.1023/A:1015393322264