Guo, YuanbinMcCain, DennisCavallaro, Joseph R.2007-10-312007-10-312005-09-012005-09-01Y. Guo, D. McCain and J. R. Cavallaro, "Hermitian Optimization and Scalable VLSI Architecture for Circulant Approximated MIMO Equalizer in CDMA Downlink," 2005.https://hdl.handle.net/1911/19940Conference PaperIn this paper, we propose a parallel and pipelined VLSI architecture for a circulant approximated equalizer for the MIMOCDMA systems. The FFT-based tap solver reduces the Direct-Matrix-Inverse of the size (NF x NF) to the inverse of O(N) sub-matrices of the size (N x N). Hermitian optimization and tree pruning is proposed to reduce the number and complexity of the FFTs. A divide-andconquer method partitions the 4£4 sub-matrices into 2x2 sub-matrices and simplifies the inverse of sub-matrices. Generic VLSI architecture is derived to eliminate the redundancies in the complex operations. Multiple level parallelism and pipelining is investigated with a Catapult C High-Level-Synthesis (HLS) methodology. This leads to efficient VLSI architectures with 3x further complexity reduction. The scalable VLSI architectures are prototyped with the Xilinx FPGAs and achieve area/time efficiency.engMIMOCDMAchip equalizerHermitian optimizationConference paperMIMOCDMAchip equalizerHermitian optimizationhttp://dx.doi.org/10.1109/VETECF.2005.1558489