Radosavljevic, Predragde Baynast, AlexandreKarkooti, MarjanCavallaro, Joseph R.2007-10-312007-10-312006-02-012006-02-01P. Radosavljevic, A. de Baynast, M. Karkooti and J. R. Cavallaro, "High-Throughput Multi-rate LDPC Decoder based on Architecture-Oriented Parity-Check Matrices," 2006.https://hdl.handle.net/1911/20209Conference PaperHigh throughput pipelined LDPC decoder that supports multiple code rates and codeword sizes is proposed. In order to increase memory throughput, irregular block structured parity-check matrices are designed with the constraint of equally distributed odd and even nonzero block-columns in each horizontal layer for pre-determined set of code rates. Designed decoder achieves data throughput of approximately 1 Gb/s without sacrificing error-correcting performance of capacity-approaching irregular block codes. The prototype architecture is implemented on FPGA.engBlock-structured LDPC codeslayered belief propgationarchitecture-oriented design of parity-check matricesflexible high-throughput architecturepipelining of horizontal layersFPGA implementationConference paperBlock-structured LDPC codeslayered belief propgationarchitecture-oriented design of parity-check matricesflexible high-throughput architecturepipelining of horizontal layersFPGA implementation