2019-03-292019-03-292019-02-12Aggrawal, Himanshu and Babakhani, Aydin, "Impulse sampler architecture and active clock cancellation architecture." Patent US10204697B2. issued 2019-02-12. Retrieved from <a href="https://hdl.handle.net/1911/105262">https://hdl.handle.net/1911/105262</a>.https://hdl.handle.net/1911/105262A novel nonlinear impulse sampler is presented that provides a clock sharpening circuit, sampling stage, and post-sampling block. The clock sharpening circuit sharpens the incoming clock while acting as a buffer, and the sharpened clock is fed to the input of the sampling stage. The impulse sampling stage has two main transistors, where one transistor generates the impulse and the other transistor samples the input signal. Post-sampling block processes the sampled signal and acts as a sample and hold circuit. The architecture uses an ultrafast transmission-line based inductive peaking technique to turn on a high-speed sampling bipolar transistor for a few picoseconds. It is shown that the sampler can detect impulses as short as 100 psec or less.16engUtility patentUS10204697B2