Sun, YangZhu, YumingGoel, ManishCavallaro, Joseph R.2012-06-132012-06-132008-07-01Y. Sun, Y. Zhu, M. Goel and J. R. Cavallaro, "Configurable and Scalable High Throughput Turbo Decoder Architecture for Multiple 4GWireless Standards," 2008.http://scholar.google.com/scholar?cluster=793314942826133761&hl=en&as_sdt=0,44https://hdl.handle.net/1911/64264In this paper, we propose a novel multi-code turbo decoder architecture for 4G wireless systems. To support various 4G standards, a configurable multi-mode MAP (maximum a posteriori) decoder is designed for both binary and duo-binary turbo codes with small resource overhead (less than 10%) compared to the single-mode architecture. To achieve high data rates in 4G, we present a parallel turbo decoder architecture with scalable parallelism tailored to the given throughput requirements. High-level parallelism is achieved by employing contention-free interleavers. Multi-banked memory structure and routing network among memories and MAP decoders are designed to operate at full speed with parallel interleavers. We designed a very low-complexity recursive on-line address generator supporting multiple interleaving patterns, which avoids the interleaver address memory. Design trade-offs in terms of area and power efficiency are explored to find the optimal architectures. A 711 Mbps data rate is feasible with 32 Radix-4 MAP decoders running at 200 MHz clock rate.engClock rateMulti-code turbo decoderInterleaverConference paperhttp://dx.doi.org/10.1109/ASAP.2008.4580180