Karkooti, MarjanCavallaro, Joseph R.Dick, Chris2007-10-312007-10-312005-10-012005-10-01M. Karkooti, J. R. Cavallaro and C. Dick, "FPGA Implementation of Matrix Inversion Using QRD-RLS Algorithm," 2005.https://hdl.handle.net/1911/20002Conference PaperThis paper presents a novel architecture for matrix inversion by generalizing the QR decomposition-based recursive least square (RLS) algorithm. The use of Squared Givens rotations and a folded systolic array makes this architecture very suitable for FPGA implementation. Input is a 4 Ã 4 matrix of complex, floating point values. The matrix inversion design can achieve throughput of 0.13M updates per second on a state of the art Xilinx Virtex4 FPGA running at 115 MHz. Due to the modular partitioning and interfacing between multiple Boundary and Internal processing units, this architecture is easily extendable for other matrix sizes.engQRD implementationSquared Givens RotationConference paperQRD implementationSquared Givens Rotationhttp://dx.doi.org/10.1109/ACSSC.2005.1600043