Karkooti, MarjanCavallaro, Joseph R.2007-10-312007-10-312004-04-012004-04-01M. Karkooti and J. R. Cavallaro, "Semi-parallel Reconfigurable Architectures for Real-time LDPC Decoding," vol. 1, 2004.https://hdl.handle.net/1911/19999Conference PaperThis paper presents a semi-parallel architecture for decoding Low Density Parity Check (LDPC) codes. A modified version of Min-Sum algorithm has been used which has the advantage of simpler computations compared to Sum-Product algorithm without any loss in performance. Special structure of the parity check matrix of the proposed code leads to an efficient semi-parallel implementation of the decoder for a family of (3,6) LDPC codes. A prototype architecture has been implemented in VHDL on programmable hardware. The design is easily scalable and reconfigurable for larger block sizes. Simulation results show that our proposed decoder for a block length of 1536 bits can achieve data rates up to 127 Mbps.engReconfigurable architectureFPGA implementationChannel codingParallel architectureArea-time tradeoffsConference paperReconfigurable architectureFPGA implementationChannel codingParallel architectureArea-time tradeoffshttp://dx.doi.org/10.1109/ITCC.2004.1286526