Rajagopal, SridharRixner, ScottCavallaro, Joseph R.2007-10-312007-10-312002-08-202002-08-20S. Rajagopal, S. Rixner and J. R. Cavallaro, "A programmable baseband processor design for software defined radios," vol. 3, 2002.https://hdl.handle.net/1911/20233Conference PaperFuture wireless systems need extremely fast and flexible architectures to support varying standards, algorithms and protocols with data rates in the range of 10-100 Mbps. Software Defined Radios (SDRs) based on DSP-FPGAs are a widely proposed solution for these systems. However, these SDR solutions have not been able to meet real-time requirements. We propose a programmable architecture solution for SDRs using a stream-based architecture based on the <i>Imagine</i> media processor. The configurable <i>Imagine</i> simulator allows us to investigate issues such as memory bottlenecks, number and type of functional units needed, and the utilization of those functional units. To evaluate stream-based architectures for baseband processing, we parallelize and implement sophisticated baseband algorithms including multiuser estimation, multiuser detection and Viterbi decoding on this simulator. We present the bottlenecks in such a stream-based architecture for efficient communications processing. Comparisons with current generation DSP-based solutions show orders-of-magnitude performance improvements, both due to the stream-based nature of computations as well as the increase in the number of functional units having a high utilization factor. The result is a baseband processor designed with broad system functionality and flexibility that approaches real-time performance for future wireless systems.engcommunications processormultiuser estimationmultiuser detectionViterbi decodingConference papercommunications processormultiuser estimationmultiuser detectionViterbi decodinghttp://dx.doi.org/10.1109/MWSCAS.2002.1187061