Yang, Kaiyuan2025-05-162024-122025-02-03December 2https://hdl.handle.net/1911/118351This thesis presents a miniaturized neural implant with magnetoelectric power and wireless communication. The analog front end (AFE) design consists of a low-noise amplifier (LNA), a noise-shaping SAR ADC, and a digital post-processing block. Conventionally, the first stage is a high-gain LNA to maximize energy efficiency. However, the motion/stimulation artifacts cause the LNA saturation issue. Recently, more papers have presented ADC-only structures to address this issue. Although ADC-only structures can achieve high energy efficiency, the energy and area efficiency of the system are limited due to the high oversampling ratio (OSR). The proposed design achieves the lowest OSR with comparable noise performance and input range among recent works. For the implant’s wireless uplink communication, we propose adopting energy extraction techniques to enhance the SNR and increase the data rate. The implant SoC is fabricated using standard TSMC 180-nm CMOS technology. The SoC chip has an active area of 2.6 mm2, and the AFE has an active area of 0.372 mm2 with 6.16 µW power consumption. The AFE achieves 8µVrms noise at the AP band and 11.35 µVrms noise at the LFP band. The wireless uplink communication achieves a 17.73 kbps data rate with 0.9pJ/bit energy efficiency. The chip is validated through an in-vitro test demonstrating the LFP recording, wireless power transfer, and communication.application/pdfenAnalog Front EndNeural RecordingNeural ImplantThesis2025-05-16