Guo, YuanbinMcCain, DennisCavallaro, Joseph R.2007-10-312007-10-312004-05-012004-05-01Y. Guo, D. McCain and J. R. Cavallaro, "Low Complexity System-On-Chip Architectures Of Optimal Parallel-Residue-Compensation In CDMA Systems," vol. 4, no. 4, 2004.https://hdl.handle.net/1911/19926Conference PaperIn this paper, we propose a novel multi-stage Parallel-Residue-Compensation (PRC) receiver architecture for enhanced suppression of the MAI in CDMA systems. We extract the commonality to avoid the direct Interference Cancellation and reduce the algorithm complexity from O(K²N) to O(KN). In the second part, scalable VLSI architectures are implemented in a FPGA prototyping system with an efficient Precision-C System-on-Chip (SOC) design methodology. Hardware efficiency is achieved by investigating multi-level parallelism and pipelines. The design of Sum-Sub-MUX Unit (SMU) combinational logic avoids the usage of dedicated multipliers with at least 10X saving in hardware resources. The most area/timing efficient design only uses area similar to the most area constraint architecture but gives at least 4X speedup over a conventional design.engSystem-On-ChipParallel-Residue-CompensationInterference CancellationCDMAConference paperSystem-On-ChipParallel-Residue-CompensationInterference CancellationCDMA