Sun, YangCavallaro, Joseph R.2012-06-132012-06-132008-09-01Y. Sun and J. R. Cavallaro, "A LOW-POWER 1-Gbps RECONFIGURABLE LDPC DECODER DESIGN FOR MULTIPLE 4G WIRELESS STANDARDS," 2008.http://scholar.google.com/scholar?cluster=17679370312231082906&hl=en&as_sdt=0,44https://hdl.handle.net/1911/64263In this paper we present an efficient system-on-chip implementation of a 1-Gbps LDPC decoder for 4G (or beyond 3G) wireless standards. The decoder has a scalable data path and can be dynamically reconfigured to support multiple 4G standards. We utilize a pipelined version of the layered belief propagation algorithm to achieve partial-parallel decoding of structured LDPC codes. Instead of using the sub-optimal Minsum algorithm, we propose to use the powerful belief propagation (BP) decoding algorithm by designing an area-efficient soft-input soft-output (SISO) decoder. Two power saving schemes are employed to reduce the power consumption up to 65%. The decoder has been synthesized, placed, and routed on a TSMC 90nm 1.0V 8-metal layer CMOS technology with a total area of 3.5 mm2. The maximum clock frequency is 450 MHz and the estimated peak power consumption is 410 mW.engLDPC decoderWireless systemsCMOSPipelinedSISO decoderBest Paper AwardConference paperhttp://dx.doi.org/10.1109/SOCC.2008.4641546