<?xml version="1.0" encoding="UTF-8"?><?xml-stylesheet type="text/xsl" href="static/style.xsl"?><OAI-PMH xmlns="http://www.openarchives.org/OAI/2.0/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/ http://www.openarchives.org/OAI/2.0/OAI-PMH.xsd"><responseDate>2026-09-21T15:55:18Z</responseDate><request verb="GetRecord" identifier="oai:repository.rice.edu:1911/17116" metadataPrefix="dim">https://repository.rice.edu/server/oai/request</request><GetRecord><record><header><identifier>oai:repository.rice.edu:1911/17116</identifier><datestamp>2024-01-11T20:56:39Z</datestamp><setSpec>com_1911_8299</setSpec><setSpec>col_1911_13110</setSpec></header><metadata><dim:dim xmlns:dim="http://www.dspace.org/xmlns/dspace/dim" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:doc="http://www.lyncode.com/xoai" xsi:schemaLocation="http://www.dspace.org/xmlns/dspace/dim http://www.dspace.org/schema/dim.xsd">
   <dim:field mdschema="dc" element="contributor" qualifier="advisor">Adve, Sarita V.</dim:field>
   <dim:field mdschema="dc" element="creator">Pai, Vijay Sadananda</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="accessioned">2009-06-04T08:18:20Z</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="available">2009-06-04T08:18:20Z</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="issued">1997</dim:field>
   <dim:field mdschema="dc" element="identifier" qualifier="citation">Pai, Vijay Sadananda. &amp;quot;The impact of instruction-level parallelism on multiprocessor performance and simulation methodology.&amp;quot; (1997) Master’s Thesis,  Rice University.  &amp;lt;a href=&amp;quot;https://hdl.handle.net/1911/17116&amp;quot;&amp;gt;https://hdl.handle.net/1911/17116&amp;lt;/a&amp;gt;.</dim:field>
   <dim:field mdschema="dc" element="identifier" qualifier="uri">https://hdl.handle.net/1911/17116</dim:field>
   <dim:field mdschema="dc" element="identifier" qualifier="callno">THESIS E.E. 1997 PAI</dim:field>
   <dim:field mdschema="dc" element="description" qualifier="abstract">Current microprocessors exploit high levels of instruction-level parallelism (ILP). This thesis presents the first detailed analysis of the impact of such processors on shared-memory multiprocessors.
We find that ILP techniques substantially reduce CPU time in multiprocessors, but are less effective in reducing memory stall time for our applications. Consequently, despite the latency-tolerating techniques incorporated in ILP processors, memory stall time becomes a larger component of execution time and parallel efficiencies are generally poorer in our ILP-based multiprocessor than in an otherwise equivalent previous-generation multiprocessor. We identify clustering independent read misses together in the processor instruction window as a key optimization to exploit the ILP features of current processors.
We also use the above analysis to examine the validity of direct-execution simulators with previous-generation processor models to approximate ILP-based multiprocessors. We find that, with appropriate approximations, such simulators can reasonably characterize the behavior of applications with poor overlap of read misses. However, they can be highly inaccurate for applications with high overlap of read misses.</dim:field>
   <dim:field mdschema="dc" element="format" qualifier="extent" lang="en_US">57 p.</dim:field>
   <dim:field mdschema="dc" element="format" qualifier="mimetype">application/pdf</dim:field>
   <dim:field mdschema="dc" element="language" qualifier="iso">eng</dim:field>
   <dim:field mdschema="dc" element="rights">Copyright is held by the author, unless otherwise indicated. Permission to reuse, publish, or reproduce the work beyond the bounds of fair use or other exemptions to copyright law must be obtained from the copyright holder.</dim:field>
   <dim:field mdschema="dc" element="subject">Electronics</dim:field>
   <dim:field mdschema="dc" element="subject">Electrical engineering</dim:field>
   <dim:field mdschema="dc" element="subject">Computer science</dim:field>
   <dim:field mdschema="dc" element="title">The impact of instruction-level parallelism on multiprocessor performance and simulation methodology</dim:field>
   <dim:field mdschema="dc" element="type">Thesis</dim:field>
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   <dim:field mdschema="thesis" element="degree" qualifier="department">Electrical Engineering</dim:field>
   <dim:field mdschema="thesis" element="degree" qualifier="discipline">Engineering</dim:field>
   <dim:field mdschema="thesis" element="degree" qualifier="grantor">Rice University</dim:field>
   <dim:field mdschema="thesis" element="degree" qualifier="level">Masters</dim:field>
   <dim:field mdschema="thesis" element="degree" qualifier="name">Master of Science</dim:field>
   <dim:field mdschema="others" element="access-status">open.access</dim:field>
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