Partitioned register-set architectures pose a challenge to standard scheduling algorithms. To create an efficient schedule, an instruction scheduler for such an architecture must consider the location of an operand in the register file, the availability of the inter-cluster data bus, and the profitability of a inter-cluster copy instruction. This technical report presents the implementation of the Top-Down Close scheduling instruction for the Texas Instrument's TMS320C6211 architecture. The report discusses the modifications required to implement the algorithm on the architecture and the results of running the algorithm on benchmarks.