VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes
| dc.citation.conferenceDate | 2007 | en_US |
| dc.citation.conferenceName | IEEE International Symposium on Circuits and Systems (ISCAS) | en_US |
| dc.citation.firstpage | 2104 | |
| dc.citation.lastpage | 2107 | |
| dc.citation.location | New Orleans, LA | en_US |
| dc.contributor.author | Sun, Yang | |
| dc.contributor.author | Karkooti, Marjan | |
| dc.contributor.author | Cavallaro, Joseph R. | |
| dc.contributor.org | Center for Multimedia Communication | en_US |
| dc.date.accessioned | 2012-06-14T15:22:39Z | |
| dc.date.available | 2012-06-14T15:22:39Z | |
| dc.date.issued | 2007-05-01 | eng |
| dc.description.abstract | A low-density parity-check (LDPC) decoder architecture that supports variable block sizes and multiple code rates is presented. The proposed architecture is based on the structured quasi-cyclic (QC-LDPC) codes whose performance compares favorably with that of randomly constructed LDPC codes for short to moderate block sizes. The main contribution of this work is to address the variable block-size and multirate decoder hardware complexity that stems from the irregular LDPC codes. The overall decoder, which was synthesized, placed and routed on TSMC 0.13-micron CMOS technology with a core area of 4.5 square millimeters, supports variable code lengths from 360 to 4200 bits and multiple code rates between 1/4 and 9/10. The average throughput can achieve 1 Gbps at 2.2 dB SNR. | en_US |
| dc.description.sponsorship | Nokia | en_US |
| dc.description.sponsorship | National Science Foundation | en_US |
| dc.identifier.citation | Y. Sun, M. Karkooti and J. R. Cavallaro, "VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes," 2007. | * |
| dc.identifier.doi | http://dx.doi.org/10.1109/ISCAS.2007.378514 | en_US |
| dc.identifier.other | http://scholar.google.com/scholar?cluster=12322474661063382493&hl=en&as_sdt=0,44 | |
| dc.identifier.uri | https://hdl.handle.net/1911/64266 | |
| dc.language.iso | eng | en |
| dc.publisher | IEEE | en_US |
| dc.subject | Low density parity-check (LDPC) | en_US |
| dc.subject | Quasi-cyclic codes (QC-LDPC) | en_US |
| dc.subject | Block-size | en_US |
| dc.subject | Multirate decoder | en_US |
| dc.subject | Throughput | en_US |
| dc.title | VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes | en_US |
| dc.type | Conference paper | en_US |
| dc.type.dcmi | Text | en |
| dc.type.dcmi | Text | en_US |