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\begin{abstract}
Ever increasing demand for high data rate wireless transmissions with high spectral efficiency leads to utilization of communication systems with multiple transmit and receive antennas. In addition, excellent error-rate performance can be achieved with iterative receiver structure composed of inner detection and outer decoding. In this work we design algorithms and architectures for iterative wireless receivers with multiple antennas that are applied in both downlink and uplink scenarios. It is our goal to develop wireless receivers with implementable hardware cost, excellent error-rate performance while achieving high data rates in the order of 1 Gbps.

Soft sphere detection algorithm with reduced computational complexity based on probabilistically bounded candidate-search process is proposed. The error-rate performance are improved compare to other bounded soft sphere detection schemes for the same hardware cost. Partial candidate-search process called QRD-QLD detection is also developed for fast mobile downlink receivers. It has significantly smaller detection latency than the well-known QRD-M algorithm proposed for several emerging wireless systems. The error-rate performance are equivalent for identical hardware complexity. We apply bounded soft sphere detection in the single-carrier uplink receiver specified for the 3GPP-LTE wireless standard. By applying sphere post-detection after MMSE-based channel pre-equalization, the interference from multiple users is successfully suppressed with limited increase of computational complexity. Cost-efficient high-speed architecture design of soft sphere detector based on bounded candidate-search has been also implemented. 

Outer LDPC decoding is used at the receiver back-end. Different levels of processing parallelism for outer structured semi-parallel LDPC decoders are investigated. We propose estimation methodology that quickly and accurately determines decoder architecture with the best tradeoff between area cost, decoding throughput and error-rate performance. Two decoder architectures with different levels of processing parallelism are implemented. Block-structured LDPC codes are designed for particular inner soft sphere detector and channel environment supporting modular high-speed decoder architectures. Finally, we propose methodology to estimate level of processing parallelism for the physical layer portion of iterative receiver necessary to achieve real-time data-rates of future wireless systems, such as the 1 Gbps downlink transmission.
\end{abstract}


